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ksz8842-16/32 mql/mvl/mvli/mbl 2-port ethernet switch with non-pci interface data sheet rev 1.9 linkmd is a registered trademark of micrel, inc. product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies october 2007 1 m9999-102207-1.9 general description the ksz8842-series of 2-port switches includes pci and non-pci cpu interfaces, and are available in 8/16-bit and 32-bit bus designs (see ordering information ). this datasheet describes the ksz8842m-series of non- pci cpu interface chips. for information on the ksz8842 pci cpu interface switches, refer to the ksz8842p datasheet. the ksz8842m is the industrys first fully managed, 2- port switch with a non-pci cpu interface. it is based on a proven, 4 th generation, integrated layer-2 switch, compliant with ieee 802.3u standards. also an industrial temperature grade version of the ksz8842, the ksz8842mvli, can be ordered (see ordering information ). the ksz8842m can be configured as a switch or as a low-latency ( 310 nanoseconds) repeater in latency- critical, embedded or industrial ethernet applications. for industrial applications, the ksz8842m can run in half-duplex mode regardless of the application. linkmd ? the ksz8842m offers an extensive feature set that includes tag/port-based vlan, quality of service (qos) priority management, management information base (mib) counters, and cpu control/data interfaces to effectively address fast ethernet applications. the ksz8842m contains: two 10/100 transceivers with patented, mixed-signal, low-power technology, two media access control (mac) units, a direct memory access (dma) channel, a high-speed, non-blocking, switch fabric, a dedicated 1k entry forwarding table, and an on-chip frame buffer memory. functional diagram p1 h p a u t o md i / md i - x p2 h p a u t o md i / md i - x e m b e d d e d p r o c e s s o r i n t e r f a c e 1k l o ok - u p en g i n e s c he du l i n g m a nag em en t b u ffe r m a n age m e nt fr a m e b u ffe r s fifo, flow control, vlan tagging ,priority 10 / 1 00 ma c 1 10 / 1 00 ma c 2 sw i t c h ho s t ma c 1 0 / 1 00 b a s e - t/ t x ph y 1 1 0 / 1 00 b a s e - t/ t x ph y 2 eepr o m in te r f a c e le d dr i v e r s mi b co u n t e r s p 1 le d [ 3: 0] p 2 le d [ 3: 0] eep r o m i / f n on- p c i cp u bu s in t e r f a c e un i t qm u dm a c h an ne l co n t r o l r e gi s t er s rx q 4k b 8 , 16 , or 32 - b i t g e n e r i c h o st in te r f a c e tx q 4k b figure 1. ksz8842m functional diagram downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 2 m9999-102207-1.9 features switch management ? non-blocking switch fabric assures fast packet delivery by utilizing a 1k entry forwarding table ? fully compliant with ieee 802.3u standards ? full-duplex ieee 802.3x flow control (pause) with force mode option ? half-duplex back pressure flow control advanced switch management ? ieee 802.1q vlan support for up to 16 groups (full range of vlan ids) ? vlan id tag/untag options, on a per port basis ? ieee 802.1p/q tag insertion or removal on a per port basis (egress) ? programmable rate limiting at the ingress and egress ports ? broadcast storm protection ? ieee 802.1d spanning tree protocol support ? mac filtering function to filter or forward unknown unicast packets ? direct forwarding mode enabling the processor to identify the ingress port and to specify the egress port ? internet group management protocol (igmp) v1/v2 snooping support for multicast packet filtering ? ipv6 multicast listener discovery (mld) snooping support monitoring ? port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port ? mib counters for fully compliant statistics gathering C 34 mib counters per port ? loopback modes for remote failure diagnostics comprehensive register access ? control registers configurable on-the-fly (port-priority, 802.1p/d/q) qos/cos packets prioritization support ? per port, 802.1p and diffserv-based ? remapping of 802.1p priority field on a per port basis power modes, packaging, and power supplies ? full-chip hardware power-down (register configuration not saved) allows low power dissipation ? per port-based, software power-save on phy (idle link detection, register configuration preserved) ? single power supply: 3.3v ? commercial temperature range: 0c to +70c ? industrial temperature range: C40c to +85c (see ordering information ) ? available in 128-pin pqfp and 100-ball lfbga (optional package: 128-pin lqfp) ? available in C16 version for 8/16-bit bus support and C 32 version for 32-bit bus support (see ordering information ) . additional features in addition to offering all of the features of an integrated layer-2 managed switch, the ksz8842m offers: ? repeater mode capabilities to allow for cut through in latency critical industrial ethernet or embedded ethernet applications ? dynamic buffer memory scheme C essential for applications such as video over ip where image jitter is unacceptable ? 2-port switch with a flexible 8, 16, or 32-bit generic host processor interfaces ? micrel linkmd ? cable diagnostics to determine cable length, diagnose faulty cables, and determine distance-to-fault ? hewlett packard (hp) auto-mdix crossover with disable and enable options ? four priority queues to handle voice, video, data, and control packets ? ability to transmit and receive jumbo frame sizes up to 1916 bytes applications ? video distribution systems ? high-end cable, satellite, and ip set-top boxes ? video over ip ? voice over ip (voip) and analog telephone adapters (ata) ? industrial control in latency critical applications ? motion control ? industrial control sensor devices (temperature, pressure, levels, and valves) ? security and surveillance cameras markets ? fast ethernet ? embedded ethernet ? industrial ethernet downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 3 m9999-102207-1.9 ordering information part number temperature range package ksz8842-16mql 0 o c to 70 o c 128-pin pqfp ksz8842-32mql 0 o c to 70 o c 128-pin pqfp KSZ8842-16MVL 0 o c to 70 o c 128-pin lqfp ksz8842-32mvl 0 o c to 70 o c 128-pin lqfp KSZ8842-16MVLi C40 o c to +85 o c 128-pin lqfp ksz8842-32mvli C40 o c to +85 o c 128-pin lqfp ksz8842-16mbl 0 o c to 70 o c 100-ball lfbga ksz8842-16mbli C40 o c to +85 o c 100-ball lfbga ksz8842-16mql-eval evaluation board for the ksz8842-16mql ksz8842-16mbl-eval evaluation board for the ksz8842-16mbl revision history revision date summary of changes 1.0 06/30/05 first released preliminary information 1.1 07/19/05 updated general description, functional diagram, pin description and features. added this revision history table, repeater mode and loopback support sections. 1.2 08/08/05 updated tables, timing and body text. 1.3 10/04/05 updated power saving bit description in p1/2phyctrl and p1/2scslmd registers 1.4 11/01/05 updated figure 16/17/18 asynchronous timing and table 24/25/26 parameters, pqfp package information 1.5 03/20/06 added qmu rx flow control high watermark qrfcr register and updated body text 1.6 11/30/06 improve the ardy low time in read cycle to 40 ns and in write cycle to 50 ns during qmu data register access 1.7 05/24/07 updated ordering information and thermal data 1.8 08/09/07 add 100 ohm resistor betw een 1.2v and 3.3v in appendix 1.9 10/22/07 add ksz8842-16mbl 100-ball bga package information downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 4 m9999-102207-1.9 content pin configuration for ksz8842-16 switches (8/16-bit) ........................................................................... ........... 11 ball configuration for ksz8842-16 switches (8/16-bit) .......................................................................... ........... 12 pin description for ksz8842-16 switches (8/16-bit) ............................................................................. ............. 13 ball description for ksz8842-16 switches (8/16-bit) ............................................................................ ............. 18 pin configuration for ksz8842-32 switches (32-bit)............................................................................. ............. 22 pin description for ksz8842-32 switches (32-bit) ............................................................................... .............. 23 functional desc ription ......................................................................................................... ................................. 28 functional overview: physical layer transceiver ................................................................................ ............. 28 100base-tx transmit ............................................................................................................ ..............................................28 100base-tx receive ............................................................................................................. ..............................................28 scrambler/de-scrambler (100base-tx only)....................................................................................... .................................28 10base-t transmit.............................................................................................................. .................................................28 10base-t receive............................................................................................................... .................................................28 power management............................................................................................................... ................................................29 mdi/mdi-x auto crossover ....................................................................................................... ............................................29 straight cable ................................................................................................................. ..................................................29 crossover cable ................................................................................................................ ...............................................30 auto negotiation ............................................................................................................... .....................................................30 linkmd cable diagnostics....................................................................................................... ..............................................31 acce ss ..............................................................................................................................................................................31 usage .......................................................................................................................... .....................................................32 functional overview: mac and switch ............................................................................................ ................... 32 address lookup.....................................................................................................................................................................32 learning....................................................................................................................... ..........................................................32 migration...................................................................................................................... ..........................................................32 aging .......................................................................................................................... ...........................................................32 forwarding..................................................................................................................... ........................................................33 switching engine ............................................................................................................... ....................................................35 mac operation.................................................................................................................. ....................................................35 inter packet gap (ipg) ......................................................................................................... .................................................35 back-off algorithm............................................................................................................. ....................................................35 late collision ................................................................................................................. ........................................................35 legal packet size.............................................................................................................. ....................................................35 flow control ................................................................................................................... .......................................................35 half-duplex backpressure ....................................................................................................... ..............................................35 broadcast storm protection..................................................................................................... ..............................................36 repeater mode.................................................................................................................. ....................................................36 clock generator ................................................................................................................ ....................................................36 bus interface unit (b iu)....................................................................................................... .................................. 36 asynchronous interface ......................................................................................................... ................................................38 synchronous interface.......................................................................................................... .................................................39 summary ...............................................................................................................................................................................39 biu implementation principles.................................................................................................. .............................................41 queue management unit (qmu) .................................................................................................... ....................... 41 transmit queue (txq) frame format.............................................................................................. .....................................41 receive queue (rxq) frame format ............................................................................................... ....................................42 advanced swit ch func tions ...................................................................................................... ........................... 44 spanning tree support.......................................................................................................... ................................................44 igmp support................................................................................................................... .....................................................45 igmp snooping ................................................................................................................ ..............................................45 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 5 m9999-102207-1.9 multicast address insertion in the static mac table .......................................................................... ............................45 ipv6 mld snooping.............................................................................................................. .................................................45 port mirroring support ......................................................................................................... ..................................................45 ieee 802.1q vlan support....................................................................................................... ...........................................45 qos priority support........................................................................................................... ...................................................46 port-based priority............................................................................................................ .....................................................46 802.1p-based priority .......................................................................................................... ..................................................46 diffserv based priority........................................................................................................ ...................................................47 rate limiting support .......................................................................................................... ..................................................47 mac filtering function ......................................................................................................... .................................................48 configuration interface ........................................................................................................ ..................................................48 eeprom interface ............................................................................................................... .................................................48 loopback su pport ............................................................................................................... ..................................................49 far-end loopba ck.............................................................................................................................................................49 near-end (remote) loopback ..................................................................................................... .....................................49 cpu interface i/o registers .................................................................................................... .............................. 51 i/o registers.................................................................................................................. ........................................................51 internal i/o space mapping ..................................................................................................... ..............................................52 register map: sw itch & mac/phy ................................................................................................. ...................... 60 bit type definition ............................................................................................................ .....................................................60 bank 0-63 bank select register (0x0e) : bsr (same location in all banks) ........................................................ ..................60 bank 0 base address register (0x00): bar ....................................................................................... ..................................60 bank 0 qmu rx flow control high watermar k configuration register (0x04): qrfcr ................................................. .....61 bank 0 bus error status register (0x06): besr .................................................................................. .................................61 bank 0 bus burst length register (0x08): bblr .................................................................................. ................................61 bank 1: reserved ............................................................................................................... ...................................................62 bank 2 host mac address register low (0x00): marl .............................................................................. .........................62 bank 2 host mac address re gister middle (0x02): marm ........................................................................... .......................62 bank 2 host mac address register high (0x04): marh............................................................................. .........................62 bank 3 on-chip bus control register (0x00): obcr............................................................................... .............................63 bank 3 eeprom control r egister (0x02): eepcr................................................................................... ............................63 bank 3 memory bist info register (0x04): mbir.................................................................................. .............................64 bank 3 global reset register (0x06): grr ....................................................................................... ...................................64 bank 3 bus configuration register (0x08): bcfg................................................................................. ................................64 banks 4 C 15: reserved ......................................................................................................... ...............................................64 bank 16 transmit control register (0x00): txcr ................................................................................. ................................65 bank 16 transmit status register (0x02): txsr .................................................................................. ................................65 bank 16 receive control register (0x04): rxcr .................................................................................. ...............................65 bank 16 txq memory information register (0x08): txmir.......................................................................... ........................66 bank 16 rxq memory information register (0x0a): rxmir.......................................................................... .......................66 bank 17 txq command regi ster (0x00): txqcr..................................................................................... ...........................67 bank 17 rxq command register (0x02): rxqcr ..................................................................................... ..........................67 bank 17 tx frame data pointer register (0x04): txfdpr .......................................................................... ........................67 bank 17 rx frame data pointer register (0x06): rxfdpr .......................................................................... .......................68 bank 17 qmu data register low (0x08): qdrl..................................................................................... ..............................68 bank 17 qmu data register high (0x0a): qdrh .................................................................................... .............................68 bank 18 interrupt enable register (0x00): ier.................................................................................. ....................................69 bank 18 interrupt status register (0x02): isr.................................................................................. .....................................70 bank 18 receive status register (0x04): rxsr ................................................................................... ................................71 bank 18 receive byte counter register (0x06): rxbc ............................................................................. ...........................72 bank 19 multicast table register 0 (0x00): mtr0 ................................................................................ ................................72 bank 19 multicast table register 1 (0x02): mtr1 ................................................................................ ................................72 bank 19 multicast table register 2 (0x04): mtr2 ................................................................................ ................................72 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 6 m9999-102207-1.9 bank 19 multicast table register 3 (0x06): mtr3 ................................................................................ ................................73 banks 20 C 31 : reserved ........................................................................................................ ..............................................73 bank 32 switch id and enable register (0x00): sider ............................................................................ ............................73 bank 32 switch global control register 1 (0x02): sgcr1 ......................................................................... ..........................73 bank 32 switch global control register 2 (0x04): sgcr2 ......................................................................... ..........................74 bank 32 switch global control register 3 (0x06): sgcr3 ......................................................................... ..........................76 bank 32 switch global control register 4 (0x08): sgcr4 ......................................................................... ..........................76 bank 32 switch global control register 5 (0x0a): sgcr5 ......................................................................... ..........................77 bank 33 switch global control register 6 (0x00): sgcr6 ......................................................................... ..........................78 bank 33 switch global control register 7 (0x02): sgcr7 ......................................................................... ..........................78 banks 34 C 38 : reserved ........................................................................................................ ..............................................78 bank 39 mac address register 1 (0x00): macar1 .................................................................................. ...........................78 bank 39 mac address register 2 (0x02): macar2 .................................................................................. ...........................79 bank 39 mac address register 3 (0x04): macar3 .................................................................................. ...........................79 bank 40 tos priority control register 1 (0x00): tosr1 .......................................................................... ............................79 bank 40 tos priority control register 2 (0x02): tosr2 .......................................................................... ............................80 bank 40 tos priority control register 3 (0x04): tosr3 .......................................................................... ............................81 bank 40 tos priority control register 4 (0x06): tosr4 .......................................................................... ............................82 bank 40 tos priority control register 5 (0x08): tosr5 .......................................................................... ............................83 bank 40 tos priority control register 6 (0x0a): tosr6.......................................................................... ............................84 bank 41 tos priority control register 7 (0x00): tosr7 .......................................................................... ............................85 bank 41 tos priority control register 8 (0x02): tosr8 .......................................................................... ............................86 bank 42 indirect access cont rol register (0x00): iacr.......................................................................... ..............................86 bank 42 indirect access data register 1 (0x02): iadr1.......................................................................... .............................87 bank 42 indirect access data register 2 (0x04): iadr2.......................................................................... .............................87 bank 42 indirect access data register 3 (0x06): iadr3.......................................................................... .............................87 bank 42 indirect access data register 4 (0x08): iadr4.......................................................................... .............................87 bank 42 indirect access data register 5 (0x0a): iadr5 .......................................................................... ............................87 bank 43: reserved .............................................................................................................. ..................................................87 bank 44 digital testing status register (0x00): dtsr.......................................................................... ...............................88 bank 44 analog testing status register (0x02): atsr........................................................................... .............................88 bank 44 digital testing control register (0x04): dtcr ......................................................................... ..............................88 bank 44 analog testing control register 0 (0x06): atcr0 ........................................................................ ..........................88 bank 44 analog testing control register 1 (0x08): atcr1 ........................................................................ ..........................88 bank 44 analog testing control register 2 (0x0a): atcr2........................................................................ ..........................88 bank 45 phy 1 mii-regist er basic control register (0x00): p1mbcr ............................................................... ..................89 bank 45 phy 1 mii-regist er basic status register (0x02): p1mbsr................................................................ ...................90 bank 45 phy 1 phyid low register (0x04): phy1ilr ............................................................................... .........................91 bank 45 phy 1 phyid high r egister (0x06): phy1ihr .............................................................................. .........................91 bank 45 phy 1 auto-negotiation advert isement register (0x08): p1anar ........................................................... ..............91 bank 45 phy 1 auto-negotiation link part ner ability register (0x0a): p1anlpr................................................... .............92 bank 46 phy 2 mii-regist er basic control register (0x00): p2mbcr ............................................................... ..................92 bank 46 phy 2 mii-regist er basic status register (0x02): p2mbsr................................................................ ...................94 bank 46 phy 2 phyid low register (0x04): phy2ilr ............................................................................... .........................94 bank 46 phy 2 phyid high r egister (0x06): phy2ihr .............................................................................. .........................95 bank 46 phy 2 auto-negotiation advert isement register (0x08): p2anar ........................................................... ..............95 bank 46 phy 2 auto-negotiation link part ner ability register (0x0a): p2anlpr................................................... .............96 bank 47 phy1 linkmd control/status (0x00): p1vct............................................................................... ...........................96 bank 47 phy1 special control/stat us register (0x02): p1phyctrl ................................................................. .................97 bank 47 phy2 linkmd control/status (0x04): p2vct............................................................................... ...........................97 bank 47 phy2 special control/stat us register (0x06): p2phyctrl ................................................................. .................98 bank 48 port 1 control register 1 (0x00): p1cr1 ................................................................................ ................................99 bank 48 port 1 control register 2 (0x02): p1cr2 ................................................................................ ..............................100 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 7 m9999-102207-1.9 bank 48 port 1 vid control register (0x04): p1vidcr............................................................................ ...........................101 bank 48 port 1 control register 3 (0x06): p1cr3 ................................................................................ ..............................101 bank 48 port 1 ingress rate control register (0x08): p1ircr.................................................................... .......................102 bank 48 port 1 egress rate control register (0x0a): p1ercr ..................................................................... ....................104 bank 49 port 1 phy special control/status, linkmd (0x00): p1scslmd............................................................. .............106 bank 49 port 1 control register 4 (0x02): p1cr4 ................................................................................ ..............................107 bank 49 port 1 status register (0x04): p1sr .................................................................................... .................................108 bank 50 port 2 control register 1 (0x00): p2cr1 ................................................................................ ..............................109 bank 50 port 2 control register 2 (0x02): p2cr2 ................................................................................ ..............................109 bank 50 port 2 vid control register (0x04): p2vidcr............................................................................ ...........................109 bank 50 port 2 control register 3 (0x06): p2cr3 ................................................................................ ..............................109 bank 50 port 2 ingress rate control register (0x08): p2ircr.................................................................... .......................109 bank 50 port 2 egress rate control register (0x0a): p2ercr ..................................................................... ....................109 bank 51 port 2 phy special control/status, linkmd (0x00): p2scslmd............................................................. .............110 bank 51 port 2 control register 4 (0x02): p2cr4 ................................................................................ ..............................111 bank 51 port 2 status register (0x04): p2sr .................................................................................... .................................113 bank 52 host port control register 1 (0x00): p3cr1 ............................................................................. ............................114 bank 52 host port control register 2 (0x02): p3cr2 ............................................................................. ............................114 bank 52 host port vid control register (0x04): p3vidcr ......................................................................... ........................115 bank 52 host port control register 3 (0x06): p3cr3 ............................................................................. ............................115 bank 52 host port ingress rate control register (0x08): p3ircr ................................................................. ....................115 bank 52 host port egress rate control register (0x0a): p3ercr .................................................................. ..................115 banks 53 C 63 : reserved ........................................................................................................ ............................................115 mib (management information base) counters..................................................................................... ........... 116 format of all ports dro pped packet mib counters .............................................................................. .............................117 additional mib information...................................................................................................................................................118 static mac a ddress table ....................................................................................................... ........................... 119 static mac table lookup examples: .............................................................................................. ....................................119 dynamic mac address table ...................................................................................................... ....................... 120 dynamic mac address lookup example: ............................................................................................ ...............................120 vlan table ..................................................................................................................... ...................................... 121 vlan table lookup examples:.................................................................................................... .......................................121 absolute maximum ratings (1) ............................................................................................................................. 12 2 operating ratings (1) ............................................................................................................................... .............. 122 electrical characteristics (1) ............................................................................................................................... .. 123 timing speci ficati ons .......................................................................................................... ................................ 124 asynchronous timing without usin g address strobe (adsn = 0) .................................................................... ...................124 asynchronous timing using address strobe (adsn)................................................................................ ..........................125 asynchronous timing using datacsn (ksz8842-32mql/mvl device only) .............................................................. ......126 address latching ti ming for all modes .......................................................................................... .....................................127 synchronous timing in burst write (vlbusn = 1)................................................................................. .............................128 synchronous timing in burst read (vlbusn = 1).................................................................................. ............................129 synchronous write timing (vlbusn = 0).......................................................................................... .................................130 synchronous read timing (vlbusn = 0)........................................................................................... ................................131 eeprom timing .................................................................................................................. ...............................................132 auto negotiation timing ........................................................................................................ ..............................................133 reset timing ................................................................................................................... ....................................................134 selection of isolat ion transformers............................................................................................ ....................... 135 selection of re ference crystal ................................................................................................. .......................... 135 package info rmation ............................................................................................................ ................................ 136 acronyms a nd glos sary.......................................................................................................... ............................ 139 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 8 m9999-102207-1.9 appendix ...................................................................................................................... ........................................ 141 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 9 m9999-102207-1.9 list of figures figure 1. ksz8842m functional diagram .......................................................................................... ........................................... 1 figure 2. standard C ksz8842-16 mql 128-pin pqfp (top view).................................................................... ........................ 11 figure 3. option C ksz8842-16 mvl 128-pin lqfp (top view) ...................................................................... .......................... 11 figure 4. ksz8842-16mbl 100-ball lfbga (top view).............................................................................. ............................... 12 figure 5. standard C ksz8842-32 mql 128-pin pqfp (top view).................................................................... ........................ 22 figure 6. option C ksz8842-32 mvl 128-pin lqfp (top view) ...................................................................... .......................... 22 figure 7. typical strai ght cable connection .................................................................................... ........................................... 29 figure 8. typical crosso ver cable connection ................................................................................... ........................................ 30 figure 9. auto negotiation and parallel operation .............................................................................. ........................................ 31 figure 10. destination address look up flow chart in stage one .................................................................. ............................ 33 figure 11. destination address reso lution flow chart in stage two .............................................................. ........................... 34 figure 12. mapping from isa-like, eisa-like, and vlbus-like transactions to the ksz8842m bus ................................... .......... 40 figure 13. ksz8842m 8-bit, 16-bit, and 32-bit data bus connections............................................................. .......................... 40 figure 14. 802.1p priority field format ........................................................................................ ............................................... 47 figure 15. port 2 far-end loopback path ........................................................................................ ........................................... 50 figure 16. port 1 and port 2 n ear-end (remote) loopback path................................................................... ............................. 50 figure 17. asynchronous cycle C adsn = 0....................................................................................... ...................................... 124 figure 18. asynchronous cycle C using adsn..................................................................................... .................................... 125 figure 19. asynchronous cycle C using datacsn .................................................................................. ............................... 126 figure 20. address latchi ng cycle for all modes................................................................................ ...................................... 127 figure 21. synchronous burst write cycles C vlbusn = 1......................................................................... ............................. 128 figure 22. synchronous burst read cycles C vlbusn = 1 .......................................................................... ........................... 129 figure 23. synchronous write cycle C vlbusn = 0................................................................................ ................................. 130 figure 24. synchronous read cycle C vlbusn = 0................................................................................. ................................ 131 figure 25. eeprom read cycle timing diagram .................................................................................... ................................ 132 figure 26. auto-negotiation timing............................................................................................. .............................................. 133 figure 27. re set timing ........................................................................................................ .................................................... 134 figure 28. 128-pin pqfp package.figur e 29. optional 128- pin lqfp package ...................................................... .............. 136 figure 29. optional 128-pin lqfp package ....................................................................................... ...................................... 137 figure 30. optional 100-ball lfbga package ..................................................................................... ..................................... 138 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 10 m9999-102207-1.9 list of tables table 1. mdi/mdi-x pin definitions............................................................................................. ................................................ 29 table 2. bus interface unit signal grouping .................................................................................... ........................................... 38 table 3: transmit q ueue frame format ........................................................................................... .......................................... 41 table 4. transmit control word bit fields...................................................................................... ............................................. 42 table 5. transmit byte count format ............................................................................................ ............................................. 42 table 6. receive queue frame format ............................................................................................ .......................................... 42 table 7. frxq packet receive status............................................................................................ ............................................ 43 table 8. frxq rx byte count field .............................................................................................. ............................................. 43 table 9. spanning tree states.................................................................................................. .................................................. 44 table 10. fid+da lookup in vlan mode........................................................................................... ........................................ 46 table 11. fid+sa lookup in vlan mode ........................................................................................... ........................................ 46 table 12. eeprom format........................................................................................................ ................................................. 48 table 13. configparam word in eeprom format .................................................................................... ................................. 49 table 14. format of per port mib counters ...................................................................................... ........................................ 116 table 15. port 1 mib counter s indirect memory offset........................................................................... .................................. 117 table 16. all ports dropped packet mib counters format ....................................................................... .............................. 117 table 17. all ports dropped packet mi b counters indirect memory offsets ...................................................... .................... 117 table 18. static mac tabl e format (8 entries).................................................................................. ....................................... 119 table 19. dynamic mac address table format ( 1024 entries)...................................................................... .......................... 120 table 20. vlan table format (16 entries) ....................................................................................... ........................................ 121 table 21. maxi mum ratings...................................................................................................... ................................................ 122 table 22. operating ratings.................................................................................................... .................................................. 122 table 23. electrical characteristics ........................................................................................... ................................................ 123 table 24. asynchronous cycle (adsn = 0) timing parameters ...................................................................... ......................... 124 table 25. asynchronous cycle us ing adsn timing parameters ...................................................................... ........................ 125 table 26. asynchronous cycle us ing datacsn timing parameters ................................................................... .................... 126 table 27. address latchi ng timing parameters................................................................................... ..................................... 127 table 28. synchronous burs t write timing parameters............................................................................ ................................ 128 table 29. synchronous burs t read timing parameters ............................................................................. .............................. 129 table 30. synchronous write (vlbusn = 0) timing parameters ..................................................................... ........................ 130 table 31. synchronous read (vlbusn = 0) timing parameters ...................................................................... ....................... 131 table 32. eeprom timing parameters............................................................................................. ....................................... 132 table 33. auto negotiation timing parameters................................................................................... ...................................... 133 table 34. reset timing parameters.............................................................................................. ............................................ 134 table 35. transformer selection criteria....................................................................................... ............................................ 135 table 36. qualified si ngle port magnetic ....................................................................................... ........................................... 135 table 37. typical reference crystal characteristics............................................................................ ..................................... 135 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 11 m9999-102207-1.9 pin configuration for ksz8842-16 switches (8/16-bit) p1led2 p1led1 p1led0 p2led2 p2led1 p2led0 dgnd vddio rdyrtnn ardy p2led3 vlbusn eesk swr wrn dgnd pwrdn agnd vdda 103 bclk ncnc srdyn intrn ldevn rdn eecs cyclen dgnd vddco eeen p1led3 eedo eedi aen adsn 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vdda iset agnd nc nc nc rxp1 rxm1 agnd txp1 txm1 vddatx vddarx rxm2 rxp2 agnd txm2 txp2 vdda agnd agnd nc nc agnd vddap nc nc nc nc ncnc nc nc nc nca1 a4 a6 a8 a10 a12 a14 a15 rstn x2 ncnc vddc dgnd nc be0n be1n nc a2 a3 a5vddio dgnd a7 a9 a11 a13 x1 102 101 100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 scanen nc testen d0 d1 d2 vddio dgnd d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 nc vddio dgnd nc nc 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 6362 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 4342 41 40 39 64 ksz8842-16 mql agnd (top view) dgnd vddio figure 2. standard C ksz8842-16 mql 128-pin pqfp (top view) nc nc nc nca1 a4 a6 a8 a10 a12 a14 a15 rstn x2 ncnc vddc dgnd nc be0n be1n nc a2 a3 a5 vddio dgnd a7 a9 a11 a13 x1 p1led2 p1led1 p1led0 p2led2 p2led1 p2led0 dgnd vddio rdyrtnn ardy p2led3 vlbusn eesk swr wrn dgnd pwrdn agnd vdda 103 bclk ncnc srdyn intrn ldevn rdn eecs cyclen dgnd vddco eeen p1led3 eedo eedi aen adsn 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vdda iset agnd nc nc nc rxp1 rxm1 agnd txp1 txm1 vddatx vddarx rxm2 rxp2 agnd txm2 txp2 vdda agnd agnd nc nc agnd vddap nc nc nc nc nc nc 102 101 100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 scanen nc testen d0 d1 d2 vddio dgnd d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 nc vddio dgnd nc nc 104105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 6362 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 4342 41 40 39 64 ksz8842-16 mvl agnd (top view) dgnd vddio figure 3. option C ksz8842-16 mvl 128-pin lqfp (top view) downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 12 m9999-102207-1.9 ball configuration for ksz8842-16 switches (8/16-bit) figure 4. ksz8842-16mbl 100-ball lfbga (top view) downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 13 m9999-102207-1.9 pin description for ksz8842-16 switches (8/16-bit) pin number pin name type pin function 1 test_en i test enable for normal operation, pull-down this pin to ground. 2 scan_en i scan test scan mux enable for normal operation, pull-down this pin to ground. 3 p1led2 opu 4 p1led1 opu 5 p1led0 opu 6 p2led2 opu 7 p2led1 opu 8 p2led0 opu port 1 and port 2 led indicators 1 defined as follows: switch global control register 5: sgcr5 bit [15,9] [0,0] default [0,1] p1led3 2 /p2led3 p1led2/p2led2 link/act 100link/act p1led1/p2led1 full duplex/col 10link/act p1led0/p2led0 speed full duplex reg. sgcr5 bit [15,9] [1,0] [1,1] p1led3 2 /p2led3 act p1led2/p2led2 link p1led1/p2led1 full duplex/col p1led0/p2led0 speed notes: 1. link = on; activity = blink; link/act = on/blink; full dup/col = on/blink; full duplex = on (full duplex); off (half duplex) speed = on (100base-t); off (10base-t) 2. p1led3 is pin 27. p2led3 is pin 22. port 1 and port 2 led indicators 3 for repeater mode defined as follows: switch global control register 5: sgcr5 bit [15,9] [0,0] default [0,1] [1,0] [1,1] p1led3, p2led3 rpt_col, rpt_act p1led2, p2led2 rpt_link3/rx, rpt_err3 p1led1, p2led1 rpt_link2/rx, rpt_err2 p1led0, p2led0 rpt_link1/rx, rpt_err1 note 3: rpt_col = blink; rpt_link3/rx (host port) = on/blink; rpt_link2/rx (port 2) = on/blink; rp t_link1/rx (port 1) = on/blink; rpt_act = on if any activity, rpt_err3/2/1 = rx error on port 3, 2, or 1. 9 dgnd gnd digital ground 10 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 11 rdyrtnn ipd ready return not: for vlbus-like mode: asserted by the host to complete synchronous read cycles. if the host doesnt connect to this pin, assert this pin. for burst mode (32-bit interface only): host drives this pin low to signal waiting states. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 14 m9999-102207-1.9 pin number pin name type pin function 12 bclk ipd bus interface clock local bus clock for synchronous bus systems. maximum frequency is 50mhz. this pin should be tied low or unconnected if it is in asynchronous mode. 13 nc ipu no connect. 14 nc opu no connect. 15 srdyn opu synchronous ready not ready signal to interface with synchronous bus for both eisa-like and vlbus- like extend accesses. for vlbus-like mode, the falling edge of this signal indicates ready. this signal is synchronous to the bus clock signal bclk. for burst mode (32-bit interface only), the ksz8842m drives this pin low to signal wait states. 16 intrn opd interrupt active low signal to host cpu to indicate an interrupt status bit is set, this pin need an external 4.7k pull-up resistor. 17 ldevn opd local device not active low output signal, asserted when aen is low and a15-a4 decode to the ksz8842m address programmed into the high byte of the base address register. ldevn is a combinational decode of the address and aen signal. 18 rdn ipd read strobe not asynchronous read strobe, active low. 19 eecs opu eeprom chip select 20 ardy opd asynchronous ready ardy may be used when interfacing asynchronous buses to extend bus access cycles. it is asynchronous to the host cpu or bus clock. this pin need an external 4.7k pull-up resistor. 21 cyclen ipd cycle not for vlbus-like mode cycle signal; this pin follows the addressing cycle to signal the command cycle. for burst mode (32-bit interface only), this pin stays high for read cycles and low for write cycles. 22 p2led3 opd port 2 led indicator see the description in pins 6, 7, and 8. 23 dgnd gnd digital io ground 24 vddco p 1.2v digital core voltage output (internal 1.2v ldo power supply output), this 1.2v output pin provides power to vddc, vdda and vddap pins. note: internally generated power voltage. do not connect an external power supply to this pin. this pin is used for connecting external filter (ferrite bead and capacitors). it is recommended this pin should be connected to 3.3v power rail by a 100 ohm resistor for the internal ldo application. 25 vlbusn ipd vlbus-like mode pull-down or float: bus interface is configured for synchronous mode. pull-up: bus interface is configured for 8-bit or 16-bit asynchronous mode or eisa-like burst mode. 26 eeen ipd eeprom enable eeprom is enabled and connected when this pin is pull-up. eeprom is disabled when this pin is pull-down or no connect. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 15 m9999-102207-1.9 pin number pin name type pin function 27 p1led3 opd port 1 led indicator see the description in pins 3, 4, and 5. 28 eedo opd eeprom data out this pin is connected to di input of the serial eeprom. 29 eesk opd eeprom serial clock a 4 s (obcr[1:0]=11 on-chip bus speed @ 25 mhz) or 800 ns (obcr[1:0]=00 on-chip bus speed @ 125 mhz) serial output clock cycle to load configuration data from the serial eeprom. 30 eedi ipd eeprom data in this pin is connected to do output of the serial eeprom when eeen is pull-up. this pin can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or dont care for 32-bit bus mode when eeen is pull-down (without eeprom). 31 swr ipd synchronous write/read write/read signal for synchronous bus accesses. write cycles when high and read cycles when low. 32 aen ipu address enable address qualifier for the address decoding, active low. 33 wrn ipd write strobe not asynchronous write strobe, active low. 34 dgnd gnd digital io ground 35 adsn ipd address strobe not for systems that require address latching, the rising edge of adsn indicates the latching moment of a15-a1 and aen. 36 pwrdn ipu full-chip power-down. low = power down; high or floating = normal operation. 37 agnd gnd analog ground 38 vdda p 1.2v analog v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 39 agnd gnd analog ground 40 nc no connect 41 nc no connect 42 agnd gnd analog ground 43 vdda p 1.2v analog v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 44 nc no connect 45 rxp1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (+ differential) 46 rxm1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (C differential) 47 agnd gnd analog ground 48 txp1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (+ differential) 49 txm1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (C differential) 50 vddatx p 3.3v analog v dd input power supply with well decoupling capacitors. 51 vddarx p 3.3v analog v dd input power supply with well decoupling capacitors. 52 rxm2 i/o port 2 physical receive (mdi) or transmit (mdix) signal (- differential) 53 rxp2 i/o port 2 physical receive (mdi)or transmit (mdix) signal (+ differential) 54 agnd gnd analog ground downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 16 m9999-102207-1.9 pin number pin name type pin function 55 txm2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (- differential) 56 txp2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (+ differential) 57 vdda p 1.2 analog v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 58 agnd gnd analog ground 59 nc ipu no connect 60 nc ipu no connect 61 iset o set physical transmits output current. pull-down this pin with a 3.01k 1% resistor to ground. 62 agnd gnd analog ground 63 vddap p 1.2v analog v dd for pll input power supply from vddco (pin24) through external ferrite bead and capacitor. 64 agnd gnd analog ground 65 x1 i 66 x2 o 25mhz crystal or oscillator clock connection. pins (x1, x2) connect to a crystal. if an oscillator is used, x1 connects to a 3.3v tolerant oscillator and x2 is a no connect. note: clock requirement is 50ppm for either crystal or oscillator. 67 rstn ipu hardware reset pin (active low). this reset input is required minimum of 10ms low after stable supply voltage 3.3v. 68 a15 i address 15 69 a14 i address 14 70 a13 i address 13 71 a12 i address 12 72 a11 i address 11 73 a10 i address 10 74 a9 i address 9 75 a8 i address 8 76 a7 i address 7 77 a6 i address 6 78 dgnd gnd digital io ground 79 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 80 a5 i address 5 81 a4 i address 4 82 a3 i address 3 83 a2 i address 2 84 a1 i address 1 85 nc i no connect 86 nc i no connect 87 be1n i byte enable 1 not, active low for data byte 1 enable (dont care in 8-bit bus mode). 88 be0n i byte enable 0 not, active low for data byte 0 enable (there is an internal inverter enabled and connected to the be1n for 8-bit bus mode). 89 nc i no connect 90 dgnd gnd digital core ground 91 vddc p 1.2v digital core v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 17 m9999-102207-1.9 pin number pin name type pin function 92 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 93 nc i no connect 94 nc i no connect 95 nc i no connect 96 nc i no connect 97 nc i no connect 98 nc i no connect 99 nc i no connect 100 nc i no connect 101 nc i no connect 102 nc i no connect 103 nc i no connect 104 nc i no connect 105 nc i no connect 106 nc i no connect 107 dgnd gnd digital io ground 108 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 109 nc i no connect 110 d15 i/o data 15 111 d14 i/o data 14 112 d13 i/o data 13 113 d12 i/o data 12 114 d11 i/o data 11 115 d10 i/o data 10 116 d9 i/o data 9 117 d8 i/o data 8 118 d7 i/o data 7 119 d6 i/o data 6 120 d5 i/o data 5 121 d4 i/o data 4 122 d3 i/o data 3 123 dgnd gnd digital io ground 124 dgnd gnd digital core ground 125 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 126 d2 i/o data 2 127 d1 i/o data 1 128 d0 i/o data 0 legend: p = power supply i/o = bi-directional ipd = input with internal pull-down ipu = input with internal pull-up opd = output with internal pull-down opu = output with internal pull-up gnd = ground i = input o = output downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 18 m9999-102207-1.9 ball description for ksz8842-16 switches (8/16-bit) ball number ball name type ball function e8 test_en i test enable for normal operation, pull-down this ball to ground. d10 scan_en i scan test scan mux enable for normal operation, pull-down this ball to ground. a10 p1led2 opu b10 p1led1 opu c10 p1led0 opu a9 p2led2 opu b9 p2led1 opu c9 p2led0 opu port 1 and port 2 led indicators 1 defined as follows: switch global control register 5: sgcr5 bit [15,9] [0,0] default [0,1] p1led3 2 /p2led3 p1led2/p2led2 link/act 100link/act p1led1/p2led1 full duplex/col 10link/act p1led0/p2led0 speed full duplex reg. sgcr5 bit [15,9] [1,0] [1,1] p1led3 2 /p2led3 act p1led2/p2led2 link p1led1/p2led1 full duplex/col p1led0/p2led0 speed notes: 1. link = on; activity = blink; link/act = on/blink; full dup/col = on/blink; full duplex = on (full duplex); off (half duplex) speed = on (100base-t); off (10base-t) 2. p1led3 is ball a4. p2led3 is ball c6. port 1 and port 2 led indicators 3 for repeater mode defined as follows: switch global control register 5: sgcr5 bit [15,9] [0,0] default [0,1] [1,0] [1,1] p1led3, p2led3 rpt_col, rpt_act p1led2, p2led2 rpt_link3/rx, rpt_err3 p1led1, p2led1 rpt_link2/rx, rpt_err2 p1led0, p2led0 rpt_link1/rx, rpt_err1 note 3: rpt_col = blink; rpt_link3/rx (host port) = on/blink; rpt_link2/rx (port 2) = on/blink; rp t_link1/rx (port 1) = on/blink; rpt_act = on if any activity, rpt_err3/2/1 = rx error on port 3, 2, or 1. d9 rdyrtnn ipd ready return not: for vlbus-like mode: asserted by the host to complete synchronous read cycles. if the host doesnt connect to this ball, assert this ball. for burst mode (32-bit interface only): host drives this ball low to signal waiting states. a8 bclk ipd bus interface clock local bus clock for synchronous bus systems. maximum frequency is 50mhz. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 19 m9999-102207-1.9 ball number ball name type ball function this ball should be tied low or unconnected if it is in asynchronous mode. b8 srdyn opu synchronous ready not ready signal to interface with synchronous bus for both eisa-like and vlbus- like extend accesses. for vlbus-like mode, the falling edge of this signal indicates ready. this signal is synchronous to the bus clock signal bclk. for burst mode (32-bit interface only), the ksz8842m drives this ball low to signal wait states. c8 intrn opd interrupt active low signal to host cpu to indicate an interrupt status bit is set, this ball need an external 4.7k pull-up resistor. a7 ldevn opd local device not active low output signal, asserted when aen is low and a15-a4 decode to the ksz8842m address programmed into the high byte of the base address register. ldevn is a combinational decode of the address and aen signal. b7 rdn ipd read strobe not asynchronous read strobe, active low. c7 eecs opu eeprom chip select a6 ardy opd asynchronous ready ardy may be used when interfacing asynchronous buses to extend bus access cycles. it is asynchronous to the host cpu or bus clock. this ball needs an external 4.7k pull-up resistor. b6 cyclen ipd cycle not for vlbus-like mode cycle signal; this ball follows the addressing cycle to signal the command cycle. for burst mode (32-bit interface only), this ball stays high for read cycles and low for write cycles. c6 p2led3 opd port 2 led indicator see the description in balls a9, b9, and c9. a5 vlbusn ipd vlbus-like mode pull-down or float: bus interface is configured for synchronous mode. pull-up: bus interface is configured for 8-bit or 16-bit asynchronous mode or eisa-like burst mode. b5 eeen ipd eeprom enable eeprom is enabled and connected when this ball is pull-up. eeprom is disabled when this ball is pull-down or no connect. a4 p1led3 opd port 1 led indicator see the description in balls a10, b10, and c10. b4 eedo opd eeprom data out this ball is connected to di input of the serial eeprom. a3 eesk opd eeprom serial clock a 4 s (obcr[1:0]=11 on-chip bus speed @ 25 mhz) or 800 ns (obcr[1:0]=00 on-chip bus speed @ 125 mhz) serial output clock cycle to load configuration data from the serial eeprom. b3 eedi ipd eeprom data in this ball is connected to do output of the serial eeprom when eeen is pull- up. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 20 m9999-102207-1.9 ball number ball name type ball function this ball can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or dont care for 32-bit bus mode when eeen is pull-down (without eeprom). c3 swr ipd synchronous write/read write/read signal for synchronous bus accesses. write cycles when high and read cycles when low. a2 aen ipu address enable address qualifier for the address decoding, active low. b2 wrn ipd write strobe not asynchronous write strobe, active low. a1 adsn ipd address strobe not for systems that require address latching, the rising edge of adsn indicates the latching moment of a15-a1 and aen. b1 pwrdn ipu full-chip power-down. low = power down; high or floating = normal operation. c1 rxp1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (+ differential) c2 rxm1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (C differential) d1 txp1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (+ differential) d2 txm1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (C differential) f2 rxm2 i/o port 2 physical receive (mdi) or transmit (mdix) signal (- differential) f1 rxp2 i/o port 2 physical receive (mdi)or transmit (mdix) signal (+ differential) g2 txm2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (- differential) g1 txp2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (+ differential) h2 test2 ipu test input 2 for normal operation, left this ball open. g3 iset o set physical transmits output current. pull-down this ball with a 3.01k 1% resistor to ground. j1 x1 i k1 x2 o 25mhz crystal or oscillator clock connection. balls (x1, x2) connect to a crystal. if an oscillator is used, x1 connects to a 3.3v tolerant oscillator and x2 is a no connect. note: clock requirement is 50ppm for either crystal or oscillator. j2 rstn ipu hardware reset ball (active low). this reset input is required minimum of 10ms low after stable supply voltage 3.3v. k2 a15 i address 15 k3 a14 i address 14 j3 a13 i address 13 h3 a12 i address 12 k4 a11 i address 11 j4 a10 i address 10 h4 a9 i address 9 k5 a8 i address 8 j5 a7 i address 7 h5 a6 i address 6 k6 a5 i address 5 j6 a4 i address 4 h6 a3 i address 3 k7 a2 i address 2 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 21 m9999-102207-1.9 ball number ball name type ball function j7 a1 i address 1 h7 be1n i byte enable 1 not, active low for data byte 1 enable (dont care in 8-bit bus mode). k8 be0n i byte enable 0 not, active low for data byte 0 enable (there is an internal inverter enabled and connected to the be1n for 8-bit bus mode). k9 d15 i/o data 15 k10 d14 i/o data 14 j9 d13 i/o data 13 j10 d12 i/o data 12 j8 d11 i/o data 11 h9 d10 i/o data 10 h10 d9 i/o data 9 h8 d8 i/o data 8 g9 d7 i/o data 7 g10 d6 i/o data 6 g8 d5 i/o data 5 f9 d4 i/o data 4 f10 d3 i/o data 3 f8 d2 i/o data 2 e9 d1 i/o data 1 e10 d0 i/o data 0 c4 vddco p 1.2v digital core voltage output (internal 1.2v ldo power supply output), this 1.2v output ball provides power to all vddc/vdda balls. note: internally generated power voltage. do not connect an external power supply to this ball. this ball is used for connecting external filter (ferrite bead and capacitors). it is recommended this ball should be connected to 3.3v power rail by a 100 ohm resistor for the internal ldo application. c5 vddc p 1.2v digital core v dd input power supply from vddco (ball c4) through external ferrite bead and capacitor. d3, e3, f3 vdda p 1.2v analog v dd input power supply from vddco (ball c4) through external ferrite bead and capacitor. e1 vddatx p 3.3v analog v dd input power supply with well decoupling capacitors. e2 vddarx p 3.3v analog v dd input power supply with well decoupling capacitors. d7, e7, f7, g4, g5, g6, g7 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. d4, d5, d6, e4, e5, e6, f4, f5, f6 gnd gnd all digital and analog grounds d8, h1 nc i no connect downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 22 m9999-102207-1.9 pin configuration for ksz8842-32 switches (32-bit) p1led2 p1led1 p1led0 p2led2 p2led1 p2led0 dgnd vddio rdyrtnn ardy p2led3 vlbusn eesk swr wrn dgnd pwrdn agnd vdda 103 bclk datacsn nc srdyn intrn ldevn rdn eecs cyclen dgnd vddco eeen p1led3 eedo eedi aen adsn 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vdda iset agnd nc nc nc rxp1 rxm1 agnd txp1 txm1 vddatx vddarx rxm2 rxp2 agnd txm2 txp2 vdda agnd agnd nc nc agnd vddap d20 d21 d22 d23 d24 d25 d26 d28 d27 be2n a1 a4 a6 a8 a10 a12 a14 a15 rstn x2 d29 d30 vddcdgnd d31 be0n be1n be3n a2 a3 a5 vddio dgnd a7 a9 a11 a13 x1 102 101 100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 scanen d17 testen d0 d1 d2 vddio dgnd d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 vddio dgnd d18 d19 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 6362 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 4342 41 40 39 64 ksz8842-32 mql agnd (top view) dgnd vddio figure 5. standard C ksz8842-32 mql 128-pin pqfp (top view) d26 d28 d27 be2na1 a4 a6 a8 a10a12 a14 a15 rstn x2 d29d30 vddc dgnd d31 be0n be1nbe3n a2 a3 a5 vddio dgnd a7 a9 a11 a13 x1 p1led2 p1led1 p1led0 p2led2 p2led1 p2led0 dgnd vddio rdyrtnn ardy p2led3 vlbusn eesk swr wrn dgnd pwrdn agnd vdda 103 bclk datacsn nc srdyn intrn ldevn rdn eecs cyclen dgnd vddco eeen p1led3 eedo eedi aen adsn 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vdda iset agnd nc nc nc rxp1 rxm1 agnd txp1 txm1 vddatx vddarx rxm2 rxp2 agnd txm2 txp2 vdda agnd agnd nc nc agnd vddap d20 d21 d22 d23 d24 d25 102 101 100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 scanen d17 testen d0 d1 d2 vddio dgnd d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 vddio dgnd d18 d19 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 6362 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 4342 41 40 39 64 ksz8842-32 mvl agnd (top view) dgnd vddio figure 6. option C ksz8842-32 mvl 128-pin lqfp (top view) downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 23 m9999-102207-1.9 pin description for ksz8842-32 switches (32-bit) pin number pin name type pin function 1 test_en i test enable for normal operation, pull-down this pin to ground. 2 scan_en i scan test scan mux enable for normal operation, pull-down this pin to ground. 3 p1led2 opu 4 p1led1 opu 5 p1led0 opu 6 p2led2 opu 7 p2led1 opu 8 p2led0 opu port 1 and port 2 led indicators 1 defined as follows: switch global control register 5: sgcr5 bit [15,9] [0,0] default [0,1] p1led3 2 /p2led3 p1led2/p2led2 link/act 100link/act p1led1/p2led1 full duplex/col 10link/act p1led0/p2led0 speed full duplex reg. sgcr5 bit [15,9] [1,0] [1,1] p1led3 2 /p2led3 act p1led2/p2led2 link p1led1/p2led1 full duplex/col p1led0/p2led0 speed notes: 1. link = on; activity = blink; link/act = on/blink; full dup/col = on/blink; full duplex = on (full duplex); off (half duplex) speed = on (100base-t); off (10base-t) 2. p1led3 is pin 27. p2led3 is pin 22. port 1 and port 2 led indicators 3 for repeater mode defined as follows: switch global control register 5: sgcr5 bit [15,9] [0,0] default [0,1] [1,0] [1,1] p1led3; p2led3 rpt_col; rpt_act p1led2; p2led2 rpt_link3/rx; rpt_err3 p1led1; p2led1 rpt_link2/rx; rpt_err2 p1led0; p2led0 rpt_link1/rx; rpt_err1 note 3: rpt_col = blink; rpt_link3/rx (host port) = on/blink; rpt_link2/rx (port 2) = on/blink; rpt_link1/rx (port 1) = on/blink; rpt_act = on if any activity, rpt_err3/2/1 = rx error on port 3, 2, or 1. 9 dgnd gnd digital ground 10 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 11 rdyrtnn ipd ready return not for vlbus-like mode: asserted by the host to complete synchronous read cycles. if the host doesnt connect to this pin, assert this pin. for burst mode (32-bit interface only): host drives this pin low to signal waiting states. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 24 m9999-102207-1.9 pin number pin name type pin function 12 bclk ipd bus interface clock local bus clock for synchronous bus systems. maximum frequency is 50mhz. this pin should be tied low or unconnected if it is in asynchronous mode. 13 datacsn ipu data chip select not (for ksz8842-32 mode only) chip select signal for qmu data register (qdrh, qdrl), active low. when datacsn is low, the data path can be accessed regardless of the value of aen, a15-a1, and the content of the bank select register. 14 nc opu no connect. 15 srdyn opu synchronous ready not ready signal to interface with synchronous bus for both eisa-like and vlbus- like extend accesses. for vlbus-like mode, the falling edge of this signal indicates ready. this signal is synchronous to the bus clock signal bclk. for burst mode (32-bit interface only), the ksz8842m drives this pin low to signal wait states. 16 intrn opd interrupt active low signal to host cpu to indicate an interrupt status bit is set, this pin need an external 4.7k pull-up resistor. 17 ldevn opd local device not active low output signal, asserted when aen is low and a15-a4 decode to the ksz8842m address programmed into the high byte of the base address register. ldevn is a combinational decode of the address and aen signal. 18 rdn ipd read strobe not asynchronous read strobe, active low. 19 eecs opu eeprom chip select 20 ardy opd asynchronous ready ardy may be used when interfacing asynchronous buses to extend bus access cycles. it is asynchronous to the host cpu or bus clock. this pin need an external 4.7k pull-up resistor. 21 cyclen ipd cycle not for vlbus-like mode cycle signal; this pin follows the addressing cycle to signal the command cycle. for burst mode (32-bit interface only), this pin stays high for read cycles and low for write cycles. 22 p2led3 opd port 2 led indicator. see the description in pins 6, 7, and 8. 23 dgnd gnd digital io ground 24 vddco p 1.2v digital core voltage output (internal 1.2v ldo power supply output), this 1.2v output pin provides power to vddc, vdda and vddap pins. note: internally generated power voltage. do not connect an external power supply to this pin. this pin is used for c onnecting external filter (ferrite bead and capacitors). it is recommended this pin should be connected to 3.3v power rail by a 100 ohm resistor for the internal ldo application. 25 vlbusn ipd vlbus-like mode pull-down or float: bus interface is configured for synchronous mode. pull-up: bus interface is configured for 32-bit asynchronous mode or eisa-like burst mode. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 25 m9999-102207-1.9 pin number pin name type pin function 26 eeen ipd eeprom enable eeprom is enabled and connected when this pin is pull-up. eeprom is disabled when this pin is pull-down or no connect. 27 p1led3 opd port 1 led indicator see the description in pins 3, 4, and 5. 28 eedo opd eeprom data out this pin is connected to di input of the serial eeprom. 29 eesk opd eeprom serial clock a 4 s (obcr[1:0]=11 on-chip bus speed @ 25 mhz) or 800 ns (obcr[1:0]=00 on-chip bus speed @ 125 mhz) serial output clock cycle to load configuration data from the serial eeprom. 30 eedi ipd eeprom data in this pin is connected to do output of the serial eeprom when eeen is pull-up. this pin can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or dont care for 32-bit bus mode when eeen is pull-down (without eeprom). 31 swr ipd synchronous write/read write/read signal for synchronous bus accesses. write cycles when high and read cycles when low. 32 aen ipu address enable address qualifier for the address decoding, active low. 33 wrn ipd write strobe not asynchronous write strobe, active low. 34 dgnd gnd digital io ground 35 adsn ipd address strobe not for systems that require address latching, the rising edge of adsn indicates the latching moment of a15-a1 and aen. 36 pwrdn ipu full-chip power-down. low = power down; high or floating = normal operation. 37 agnd gnd analog ground 38 vdda p 1.2v analog v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 39 agnd gnd analog ground 40 nc no connect 41 nc no connect 42 agnd gnd analog ground 43 vdda p 1.2v analog v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 44 nc no connect 45 rxp1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (+ differential) 46 rxm1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (C differential) 47 agnd gnd analog ground 48 txp1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (+ differential) 49 txm1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (C differential) 50 vddatx p 3.3v analog v dd input power supply with well decoupling capacitors. 51 vddarx p 3.3v analog v dd 52 rxm2 i/o port 2 physical receive (mdi) or transmit (mdix) signal (- differential) 53 rxp2 i/o port 2 physical receive (mdi) or transmit (mdix) signal (+ differential) downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 26 m9999-102207-1.9 pin number pin name type pin function 54 agnd gnd analog ground 55 txm2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (- differential) 56 txp2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (+ differential) 57 vdda p 1.2 analog v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 58 agnd gnd analog ground 59 nc ipu no connect 60 nc ipu no connect 61 iset o set physical transmits output current. pull-down this pin with a 3.01k 1% resistor to ground. 62 agnd gnd analog ground 63 vddap p 1.2v analog v dd for pll input power supply from vddco (pin24) through external ferrite bead and capacitor. 64 agnd gnd analog ground 65 x1 i 25mhz crystal or oscillator clock connection. 66 x2 o pins (x1, x2) connect to a crystal. if an oscillator is used, x1 connects to a 3.3v tolerant oscillator and x2 is a no connect. note: clock is 50ppm for either crystal or oscillator. 67 rstn ipu hardware reset pin (active low). this reset input is required minimum of 10ms low after stable supply voltage 3.3v. 68 a15 i address 15 69 a14 i address 14 70 a13 i address 13 71 a12 i address 12 72 a11 i address 11 73 a10 i address 10 74 a9 i address 9 75 a8 i address 8 76 a7 i address 7 77 a6 i address 6 78 dgnd gnd digital io ground 79 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 80 a5 i address 5 81 a4 i address 4 82 a3 i address 3 83 a2 i address 2 84 a1 i address 1 85 be3n i byte enable 3 not, active low for data byte 3 enable. 86 be2n i byte enable 2 not, active low for data byte 2 enable. 87 be1n i byte enable 1 not, active low for data byte 1 enable. 88 be0n i byte enable 0 not, active low for data byte 0 enable. 89 d31 i/o data 31 90 dgnd gnd digital core ground 91 vddc p 1.2v digital core v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 27 m9999-102207-1.9 pin number pin name type pin function 92 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 93 d30 i/o data 30 94 d29 i/o data 29 95 d28 i/o data 28 96 d27 i/o data 27 97 d26 i/o data 26 98 d25 i/o data 25 99 d24 i/o data 24 100 d23 i/o data 23 101 d22 i/o data 22 102 d21 i/o data 21 103 d20 i/o data 20 104 d19 i/o data 19 105 d18 i/o data 18 106 d17 i/o data 17 107 dgnd gnd digital io ground 108 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 109 d16 i/o data 16 110 d15 i/o data 15 111 d14 i/o data 14 112 d13 i/o data 13 113 d12 i/o data 12 114 d11 i/o data 11 115 d10 i/o data 10 116 d9 i/o data 9 117 d8 i/o data 8 118 d7 i/o data 7 119 d6 i/o data 6 120 d5 i/o data 5 121 d4 i/o data 4 122 d3 i/o data 3 123 dgnd gnd digital io ground 124 dgnd gnd digital core ground 125 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 126 d2 i/o data 2 127 d1 i/o data 1 128 d0 i/o data 0 legend: p = power supply gnd = ground. i/o = bi-directional i = input o = output. ipd = input with internal pull-down. ipu = input with internal pull-up. opd = output with internal pull-down opu = output with internal pull-up. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 28 m9999-102207-1.9 functional description the ksz8842m contains two 10/100 physical layer transceivers (phys), two mac units, and a dma channel integrate d with a layer-2 switch. the ksz8842m contains a bus interface unit (biu), which controls the ksz8842m via an 8, 16, or 32-bit host inter face. physical signal transmission and reception are enhanced through the use of analog circuits in the phy that mak e the design more efficient and allow for low power consumption. functional overview: physical layer transceiver 100base-tx transmit the 100base-tx transmit function performs parallel-to-serial conversion, 4b/5b coding, scrambling, nrz-to-nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel-to-serial conversion, whic h converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding, followed by a scrambler. the serialized data is further converted from nrz-to-nrzi format, and then transmitted in mlt3 current output. the output current is set by an external1% 3.01k ? resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4ns and complies with the ansi tp-pmd standard regar ding amplitude balance, overshoot, and timing jitter. the wave-shaped 10base-t output is also incorporated into the 100base-tx transmitter. 100base-tx receive the 100base-tx receiver function performs adaptive equalization, dc restoration, mlt3-to-nrzi conversion, data and clock recovery, nrzi-to-nrz conversion, de-scrambling, 4b/5b decoding, and serial-to-parallel co nversion. the receiving side starts with the equalization filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. in this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then t unes itself for optimization. this is an ongoing process and self-adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc restoration and data conversion block. the dc restoration c ircuit is used to compensate for the effect of baseline wander and to improve the dynamic range. the differential data convers ion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this signal is sent through the de-scrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the mii format and provided as the input data to the mac. scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (emi) and baseline wander. transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (lfsr). the scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incomi ng data stream using the same sequence as at the transmitter. 10base-t transmit the 10base-t driver is incorporated with the 100base-tx driver to allow for transmission using the same magnetic. they are internally wave-shaped and pre-emphasized into outputs with a typical 2.3v amplitude. the harmonic cont ents are at least 27db below the fundamental frequency when driven by an all-ones manchester-encoded signal. 10base-t receive on the receive side, input buffers and level detecting squelch circuits are employed. a diffe rential input receiver circuit and a phase-locked loop (pll) perform the decoding function. the manchester-encoded data stream is separa ted into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv or with short pulse widt hs to prevent noise at the rxp-or-rxm input from falsely triggering the decoder. when the input exceeds the squelch limi t, the pll locks onto the incoming signal and the ksz8842m decodes a data frame. the receiver clock is maintained active durin g idle periods in between data reception. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 29 m9999-102207-1.9 power management the ksz8842m features per port power-down mode. to save power, the user can power-down the port that is not in use by setting bit 11 in either p1cr4 or p1mbcr register for port 1 and setting bit 11 in either p2cr4 or p2mbcr register for port 2. to bring the port back up, reset bit 11 in these registers. in addition, there is a full switch power-down mode. this mode shuts the entire switch down, when the pwrdn (pin 36) is pulled down to low. mdi/mdi-x auto crossover to eliminate the need for crossover cables between similar devices, the ksz8842m supports hp-auto mdi/mdi-x and ieee 802.3u standard mdi/mdi-x auto crossover. hp-auto mdi/mdi-x is the default. the auto-sense function detects remote transmit and receive pairs and correctly assigns the transmit and receive pairs for the ksz8842m device. this feature is extremely useful when end users are unaware of cable types in addition to saving on an additional uplink configuration connection. the auto-crossover feature can be disabled through the port control registers. the ieee 802.3u standard mdi and mdi-x definitions are: mdi mdi-x rj45 pins signals rj45 pins signals 1 td+ 1 rd+ 2 td- 2 rd- 3 rd+ 3 td+ 6 rd- 6 td- table 1. mdi/mdi-x pin definitions straight cable a straight cable connects an mdi device to an mdi-x device or an mdi-x device to an mdi device. the following diagram shows a typical straight cable connection between a network interface card (nic) (mdi) and a switch , or hub (mdi-x). figure 7. typical straight cable connection downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 30 m9999-102207-1.9 crossover cable a crossover cable connects an mdi device to another mdi device, or an mdi-x device to another mdi-x device. the following diagram shows a typical crossover cable connection between two switches or hubs ( two mdi-x devices). figure 8. typical crossover cable connection auto negotiation the ksz8842m conforms to the auto negotiation protocol as described by the 802.3 committee to allow the channel to operate at 10base-t or 100base-tx. auto negotiation allows unshielded twisted pair (utp) link partners to select the best common mode of operation. in auto negotiation, the link partners advertise capabilities across the link to each other. if auto negotiation is not supported or th e link partner to the ksz8842m is forced to bypass auto negotiation, the mode is set by observing the signal at the r eceiver. this is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. the link setup is shown in the following flow diagram (figure 9). downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 31 m9999-102207-1.9 start auto negotiation force link setting listen for 10base-t link pulses listen for 100base-tx idles attempt auto negotiation link mode set bypass auto negotiation and set link mode link mode set ? parallel operation join flow no yes no yes figure 9. auto negotiation and parallel operation linkmd cable diagnostics the ksz8842m linkmd uses time domain reflectometry (tdr) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. linkmd works by sending a pulse of known amplitude and duration down the mdi and mdi-x pairs and then analyzes the shape of the reflected signal. timing the pulse duration gives an indication of the distance to the cablin g fault with a maximum distance of 200m and an accuracy of +/C2m. internal circuitry displays the tdr information in a user-readable digital format in registers p1vct[8:0] or p2vct[8:0]. note: cable diagnostics are only valid for copper connections Cfiber-optic operation is not supported. access linkmd is initiated by accessing register p1vct/p2vct, the linkmd control/status register, in co njunction with register p1cr4/p2cr4, the 100base-tx phy controller register. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 32 m9999-102207-1.9 usage linkmd can be run at any time by making sure auto mdix has been disabled. to disable auto-mdix, write a 1 to p1cr4[10] for port 1 or p2cr4[10] for port 2 to enable manual control over the pair used to transmit the linkmd pulse. the self-clearing cable diagnostic test enable bit, p1vct[15] for port 1 or p2vct[15] for port 2 , is set to 1 to start the test on this pair. when bit p1vct[15] or p2vct[15] returns to 0, the test is complete. the test result is returned in bits p1vct[14:13] or p2vct[14:13] and the distance is returned in bits p1vct[8:0] or p2vct[8:0]. the cable diagnostic test results are as follows: 00 = valid test, normal condition 01 = valid test, open circuit in cable 10 = valid test, short circuit in cable 11 = invalid test, linkmd failed if p1vct[14:13]=11 or p2vct[14:13]=11, this indicates an invalid test, and occurs when the ksz8842m is unable t o shut down the link partner. in this instance, the test is not run, as it is not possible for the ksz8842m to determine if the detected signal is a reflection of the signal generated or a signal from another source. cable distance can be approximated by the following formula: p1vct[8:0] x 0.4m for port 1 cable distance p2vct[8:0] x 0.4m for port 2 cable distance this constant may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm. functional overview: mac and switch address lookup the internal lookup table stores mac addresses and their associated information. it contains a 1k entry unicast address learning table plus switching information. the ksz8842m is guaranteed to learn 1k addresses and distinguishes itself from hash-based lookup tables, which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. learning the internal lookup engine updates its table with a new entry if the following conditions are met: 1. the received packet's source address (sa) does not exist in the lookup table. 2. the received packet is good without receiving errors; the packet size is legal length. the lookup engine inserts the qualified sa into the table, along with the port number and time stamp. if the table is full, the last entry of the table is deleted to make room for the new entry. migration the internal lookup engine also monitors whether a station has moved. if a station has moved, it updates the table accordingly. migration happens when the following conditions are met: 1. the received packet's sa is in the table but the associated source port information is different. 2. the received packet is good without receiving errors; the packet size is legal length. the lookup engine updates the existing record in the table with the new source port information. aging the lookup engine updates the time stamp information of a record whenever the corresponding sa appears. the time stamp is used in the aging process. if a record is not updated for a period of time, the lookup engine removes the record from the table. the lookup engine constantly performs the aging process and continuously removes aging records. the aging period is about 200 seconds. this feature can be enabled or disabled through global register sgcr1[10]. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 33 m9999-102207-1.9 forwarding the ksz8842m forwards packets using the algorithm that is depicted in the following flowcharts. figure 10 sho ws stage one of the forwarding algorithm where the search engine looks up the vlan id, static table, and dynamic table for the destination address, and comes up with port to forward 1 (ptf1). ptf1 is then further modified by spann ing tree, igmp snooping, port mirroring, and port vlan processes to come up with port to forward 2 (ptf2), as shown in figure 11. the packet is sent to ptf2. figure 10. destination address lookup flow chart in stage one start vlan id valid? ptf1 = null search static table search complete. get ptf1 from static mac table dynamic table search search complete. get ptf1 from vlan table search complete. get ptf1 from dynamic mac table ptf1 - search vlan table - ingress vlan filtering - discard npvid check yes no found not found found not found this search is based on da or da+fid this search is based on da+fid downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 34 m9999-102207-1.9 spanning tree process ptf1 igmp process port mirror process port vlan membership check ptf2 - check receiving port's receive enable bit - check destination port's transmit enable bit - check whether packets are special (bpdu) or s p ecified - rx mirror - tx mirror - rx or tx mirror - rx and tx mirror - applied to mac #1 and mac #2 - igmp will be forwarded to the host port figure 11. destination address resolution flow chart in stage two the ksz8842m will not forward the following packets: 1. error packets. these include framing errors, frame check sequence (fcs) errors, alignment errors, and illegal size packet errors. 2. 802.3x pause frames. the ksz8842m intercepts these packets and performs the flow control. 3. "local" packets. based on destination address (da) lookup. if the destination port from the lookup table matches the port from which the packet originated, the packet is defined as "local." downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 35 m9999-102207-1.9 switching engine the ksz8842m features a high-performance switching engine to move data to and from the macs packet buffers. it operates in store and forward mode, while the efficient switching mechanism reduces overall latency. the switching engine has a 32kb internal frame buffer. this resource is shared between all the ports. there are a total of 256 buffers available. each buffer is sized at 128b. mac operation the ksz8842m strictly abides by ieee 802.3 standards to maximize compatibility. additionally , there is an added mac filtering function to filter unicast packets. the mac filtering function is useful in applications such as voip where restricting certain packets reduces congestion and thus improves performance. inter packet gap (ipg) if a frame is successfully transmitted, the minimum 96-bit time for ipg is measured between two consecutive pac kets. if the current packet is experiencing collisions, the minimum 96-bit time for ipg is measured from carrier sense (crs) to the next transmit packet. back-off algorithm the ksz8842m implements the ieee standard 802.3 binary exponential back-off algorithm in half-duplex mode, and optional "aggressive mode" back-off. after 16 collisions, the packet is optionally dropped depending on the swit ch configuration in sgcr1[8]. late collision if a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped. legal packet size the ksz8842m discards packets less than 64 bytes and can be programmed to accept packet size up to 1536 bytes in sgcr2[1]. the ksz8842m can also be programmed for special applications to accept packet size up to 1916 bytes in sgcr2[2]. flow control the ksz8842m supports standard 802.3x flow control frames on both transmit and receive sides. on the receive side, if the ksz8842m receives a pause control frame, the ksz8842m will not transmit the next normal frame until the timer, specified in the pause control frame, expires. if another pause frame is received b efore the current timer expires, the timer will be updated with the new value in the second pause frame. during this period (while it is flow controlled), only flow control packets from the ksz8842m are transmitted. on the transmit side, the ksz8842m has intelligent and efficient ways to determine when to invoke flow control. the flow control is based on availability of the system resources, including available buffer s, available transmit queues, and available receive queues. the ksz8842m will flow control a port that has just received a packet if the destination port resource is busy. the ksz8842m issues a flow control frame (xoff), containing the maximum pause time defined in ieee standard 802.3x. o nce the resource is freed up, the ksz8842m sends out the other flow control frame (xon) with zero pause time to turn off the flow control (turn on transmission to the port). a hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated. the ksz8842m flow controls all ports if the receive queue becomes full. half-duplex backpressure a half-duplex backpressure option (not in ieee 802.3 standards) is also provided. the activation and deactivation conditions are the same in full-duplex mode. if backpressure is required, the ksz8842m sends preambles to defer the other stations' transmission (carrier sense deference). downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 36 m9999-102207-1.9 to avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the ksz8842m discontinues the carrier sense and then raises it again quickly. this short silent time (no carrier sense) preve nts other stations from sending out packets thus keeping other stations in a carrier sense deferred state. if the port has packets to send during a backpressure situation, the carrier sense type backpressure is interrupted and thos e packets are transmitted instead. if there are no additional packets to send, carrier sense type backpressure is reactivated again until switch resources free up. if a collision occurs, the binary exponential back-off algorithm is skipped and carrier sens e is generated immediately, thus reducing the chance of further collisions and carrier sense is maintained to prevent packet reception. to ensure no packet loss in 10 base-t or 100 base-tx half-duplex modes, the user must enable the following: 1. aggressive back off (bit 8 in sgcr1) 2. no excessive collision drop (bit 3 in sgcr2) note: these bits are not set in default, since this is not the ieee standard. broadcast storm protection the ksz8842m has an intelligent option to protect the switch system from receiving too many broadcast pack ets. as the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources (bandwidth and available space in transmit queues) may be utilized. the ksz8842m has the option to include multicast pac kets for storm control. the broadcast storm rate parameters are programmed globally, and can be enabled or disable d on a per port basis in p1cr1[7] and p2cr1[7]. the rate is based on a 67ms interval for 100bt and a 670ms interval f or 10bt. at the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of bytes during the interval. the rate definition is described in sgcr3[2:0][15:8]. the default setting is 0x63 (99 decimal). this is equal to a rate of 1%, calculated as follows: 148,800 frames/sec x 67 ms/interval x 1% = 99 frames/interval (approx.) = 0x63 note: 148,800 frames/sec is based on 64-byte block of packets in 100base-t with 12 bytes of ipg and 8 bytes of preamble between two packets. repeater mode when the ksz8842m is set to repeater mode (sgcr3[7] = 1), it only works on 100bt half-duplex mode. in repeater enabled mode, all ingress packets will be broadcast to the other two ports without mac address checking and learning. before setting to the repeater mode, the user has to set bit 13 (100mbps), bit 12 (auto-negotiation disabled) and bit 8 (half duplex) in both p1mbcr and p2mbcr registers as well as set bit 6 (host half duplex) in sgcr3 re gister for the repeater mode. the latency in repeater mode is defined from the 1st bit of da into the ingress port 1 to the 1st bit of da out of the egress port 2. the minimum is 270 ns and the maximum is 310 ns (one clock skew of 25 mhz between tx and rx). clock generator the x1 and x2 pins are connected to a 25 mhz crystal. x1 can also serve as the connector to a 3.3v, 25 mhz oscillator (as described in the pin description). the bus interface unit (biu) uses bclk (bus clock) for synchronous accesses. the maximum host por t frequency is 50 mhz for vlbus-like and burst mode (32-bit interface only). bus interface unit (biu) the host interface of the biu is designed to communicate with embedded processors. the host interface of the ksz8842m is a generic bus interface. some glue logic may be required when the interface talks to various buses and processors. in terms of transfer type, the biu can support two transfers: asynchronous transfer and synchronous transfer. to support these transfers (asynchronous and synchronous), the biu provides three groups of signals: 1. synchronous signals 2. asynchronous signals 3. common signals are used for both synchronous and asynchronous transfers. since both synchronous and asynchronous signals are independent of each other, synchronous burst transfer and asynchronous transfer can be mixed or interleaved but cannot be overlapped (due to the sharing of the common signals). in terms of physical data bus size, the ksz8842m supports 8, 16, and 32 bit host/industrial standard data bus sizes. given a physical data bus size, the ksz8842m supports 8, 16, or 32-bit data transfers depending on the size of the downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 37 m9999-102207-1.9 physical data bus. for example, for a 32-bit system/host data bus, it allows 8, 16, and 32-bit data transfers (ksz8842- 32mql); for a 16-bit system/host data bus, it allows 8 and 16-bit data transfers (ksz8842-16mql); and for 8-bit system/host data bus, it only allows 8-bit data transfers (ksz8842-16mql). note that ksz8842m does not support internal data byte-swap but it does support internal data word-swap. this m eans that the system/host data bus hd[7:0] has to connect to both d[7:0] and d[15:8] for 8-bit data bus interfaces. however, the system/host data bus hd[15:8] and hd[7:0] just connects to d[15:8] and d[7:0], respectively, for 16-bit data bus interface; there is no need to connect hd[31:24] and hd[23:16] to d[31:24] and d[23:16]. table 2 describes the biu signal grouping. signal type (1) function common signals a[15:1] i address aen i address enable address enable asserted indicates memory address on the bus for dma access and since the device is an i/o device, address decoding is only enabled when aen is low. be3n, be2n, be1n, be0n i byte enable be0n be1n be2n be3n description 0 0 0 0 32-bit access (32-bit bus only) 0 0 1 1 lower 16-bit (d[15:0]) access 1 1 0 0 higher 16-bit (d[31:16]) access (32-bit bus only) 0 1 1 1 byte 0 (d[7:0]) access 1 0 1 1 byte 1 (d[15:8]) access 1 1 0 1 byte 2 (d[23:16]) access (32-bit bus only) 1 1 1 0 byte 3 (d[31:24]) access (32-bit bus only) note 1: be3n, be2n, be1n and be0n are ignored when datacsn is low because 32 bit transfers are assumed. note 2: be2n and be3n are valid only for the ksz8842-32 mode, and are nc for the ksz8842-16 mode. d[31:16] i/o data for ksz8842-32 mode only d[15:0] i/o data for both ksz8842-32 and ksz8842-16 modes adsn i address strobe the rising edge of adsn is used to latch a[15:1], aen, be3n, be2n, be1n and be0n. ldevn o local device this signal is a combinatorial decode of aen and a[15:4], the a[15:4] is used to compare against the base address register. datacsn i data register chip select (for ksz8842-32 mode only) this signal is used for central decoding architecture (mostly for embedded application). when asserted, the devices local decoding logic is ignored and the 32-bit access to qmu data register is assumed. intrn o interrupt synchronous transfer signals vlbusn i vlbusn = 0, vlbus-like cycle. vlbusn = 1, burst cycle (both host/system and ksz8842 can insert wait state) downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 38 m9999-102207-1.9 signal type (1) function cyclen i for vlbus-like access: used to sample swr when asserted. for burst access: used to connect to iowc# bus signal to indicate burst write. swr i write/read for vlbus-like access: used to indicate write (high) or read (low) transfer. for burst access: used to connect to iorc# bus signal to indicate burst read. srdyn o synchronous ready for vlbus-like access: exactly the same signal definition of nsrdy in vlbus. for burst access: insert wait state by the ksz8842m whenever necessary during the data register access. rdyrtnn i ready return for vlbus-like access: exactly like rdyrtnn signal in vlbus to end the cycle. for burst access: exactly like exrdy signal in eisa to insert wait states. note that the wait states are inserted by system logic (memory) not by ksz8842m. bclk i bus clock asynchronous transfer signals rdn i asynchronous read wrn i asynchronous write ardy o asynchronous ready this signal is asserted (low) to insert wait states. note 1: i = input. o = output. i/o = bi-directional. table 2. bus interface unit signal grouping regardless of whether the transfer is synchronous or asynchronous, if the address latch is req uired, use the rising edge of adsn to latch the incoming signals a [15:1], aen, be3n, be2n, be1n, and be0n. note: whether the transfer is synchronous or asynchronous, if the local device decoder is used, ldevn will be asser ted to indicate that the ksz8842m is successfully targeted. basically, signal ldevn is a combinatorial d ecode of aen and a[15:4]. asynchronous interface for asynchronous transfers, the asynchronous dedicated signals rdn (for read) or wrn (for write) toggl e, but the synchronous dedicated signals bclk, cyclen, swr, and rdyrtnn are de-asserted and stay at the same logic level throughout the entire asynchronous transfer. there is no data burst support for asynchronous transfer. all asynchronous transfers are single- data transfers. the biu, however, provides flexible asynchronous interfacing to communicate with various applications and arc hitectures. three major ways of interfacing with the system (host) are. interfacing with the system/host relying on local device decoding and having stable address throughout the whole tr ansfer: 1. the typical example for this application is isa-like bus interface using latched address signals as shown in the figure 17. no additional address latch is required, therefore adsn should be connected low. the biu decodes a[15:4] and qualifies with aen (address enable) to determine if the ksz8842m switch is the intended target. t he host utilizes the rising edge of rdn to latch read data and the biu will use rising edge of wrn to latch write data. 2. interfacing with the system/host relying on local device decoding but not having stable address throughout the entire transfer: the typical example for this application is eisa-like bus (non-burst) interface as shown in the figure 18. this type of interface requires adsn to latch the address on the rising edge. the biu decodes latched a[15:4] and qualifies with aen to determine if the ksz8842m switch is the intended target. the data transfer is the same as the first case. 3. interfacing with the system/host relying on central decoding (ksz8842-32 mode only). the typical example for this application is for an embedded processor having a central decoder on the system board or within the processor. connecting the chip select (cs) from system/host to datacsn by passes the local device decoder. when the datacsn is asserted, it only allows access to the data register in 32 bits and be3n, downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 39 m9999-102207-1.9 be2n, be1n, and be0n are ignored as shown in the figure 19. no other registers can be accessed by asserting datacsn. the data transfer is the same as in the first case. independent of the type of asynchronous interface used. to insert a wait state, the biu will assert ardy to prolong the cycle. synchronous interface for synchronous transfers, the synchronous dedicated signals cyclen, swr, and rdyrtnn will to ggle but the asynchronous dedicated signals rdn and wrn are de-asserted and stay at the same logic level thr oughout the entire synchronous transfer. the synchronous interface mainly supports two applications, one for vlbus-like and the other for eis a-like (dma type c) burst transfers. the vlbus-like interface supports only single-data transfer. the pin option vlbusn determines if it is a vlbus-like or eisa-like burst transfer C if vlbusn = 0, the interface is for vlbus-like transfer; if vlbusn = 1, the interface is for eisa-like burst transfer. for vlbus-like transfer interface (vlbusn = 0): this interface is used in an architecture in which the devices local decoder is utilized; that is, the biu decodes latched a [15:4] and qualifies with aen (address enable) to determine if the switch is the intended target. no burs t is supported in this application. the m/nio signal connection in vlbus is routed to aen. the cyclen in this application is used to sample the swr signal when it is asserted. usually, cyclen is one clock delay of adsn. there is a handshaking process to end the cycle of vlbus-like transfers. when the ksz8842m is ready to finish the cycle, it asserts srdyn . the system/host acknowledges srdyn by asserting rdyrtnn after the system/host has latched the read data. the ksz8842m holds the read data until rdyrtnn is asserted. the timing waveform is shown in figures 23 and 24. for eisa-like burst transfer interface (vlbusn = 1): the swr is connected to iorc# in eisa to indicate the burst read and cyclen is connected to iowc# in eis a to indicate the burst write. note that in this application, both the system/host/memory and ksz8842m ar e capable of inserting wait states. for system/host/memory to insert a wait state, assert the rdyrtnn signal; for the ksz8842m to insert the wait state, assert the srdyn signal. the timing waveform is shown in figures 21 and 22. summary figure 12 shows the mapping from isa-like, eisa-like and vlbus-like transactions to the switchs biu. figure 13 shows the connection for different data bus sizes. for detail 8/16-bit bus signal connections and descriptions refers to application note 132. for detail 32-bit bus signal connections and descriptions refers to application note 137. note: for the 8-bit data bus mode, the internal inverter is enabled and connected between be0n and be1n, so even address will enable the be0n and odd address will enable the be1n. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 40 m9999-102207-1.9 ksz8842m biu asynchronous interface synchronous interface address latch no addr latch (adsn = 0) central decode local decode address latch central decode (vlbusn = 1) local decode (vlbusn = 0) glue logic glue logic glue logic glue logic isa eisa vlbus burst non-burst note: to use datacsn & 32-bit only for central decode figure 12. mapping from isa-like, eisa-like, and vlbus-like transactions to the ksz8842m bus d[7:0] d[15:8] d[23:16] d[31:24] gnd hd[7:0] nhbe[0] nhbe[2] nhbe[3] hd[15:8] nhbe[1] hd[23:16] hd[31:24] a[15:2] a[1] d[7:0] d[15:8] be0n be1n 8-bit data bus ha[1] ha[15:2] hd[7:0] ha[0] vdd a[15:2] a[1] d[7:0] d[15:8] be0n be1n 16-bit data bus (for example: isa-like) ha[1] ha[15:2] hd[7:0] ha[0] nsbhe a[15:2] a[1] be0n be1n be2n be3n 32-bit data bus (for example: eisa-like) ha[15:2] hd[15:8] ksz8842-16 ksz8842-16 ksz8842-32 figure 13. ksz8842m 8-bit, 16-bit, and 32-bit data bus connections downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 41 m9999-102207-1.9 biu implementation principles since the ksz8842m is an i/o device with 16 addressable locations, address decoding is based on the values of a15-a4 and aen. whenever datacsn is asserted, the address decoder is disabled and a 32-bit transfer to data register is assumed (be3n C be0n are ignored). if address latching is required, the address is latched on the rising edge of adsn and is transparent when adsn =0. 1. byte, word, and double-word data buses and accesses (transfers) are supported. 2. internal byte swapping is not implemented and word swapping is supported internally. refer to figure 13 for the appropriate 8-bit, 16-bit, and 32-bit data bus connection. 3. since independent sets of synchronous and asynchronous signals are provided, synchronous and asynchro nous cycles can be mixed or interleaved as long as they are not active simultaneously. 4. the asynchronous interface uses rdn and wrn signal strobes for data latching. if necessary, ardy is de- asserted on the leading edge of the strobe. 5. the vlbus-like synchronous interface uses bclk, adsn, and swr and cyclen to control read and write operations and generate srdyn to insert the wait state, if necessary, when vlbusn = 0. for read, the data must be held until rdyrtnn is asserted. 6. the eisa-like burst transfer is supported using synchronous interface signals and datacsn when i/o signal vlbusn = 1. both the system/host/memory and ksz8842m are capable of inserting wait states. to set the system/host/memory to insert a wait state, assert rdyrtnn signal. to set the ksz8842m to insert a wait st ate, assert srdyn signal. queue management unit (qmu) the queue management unit (qmu) manages packet traffic between the mac/phy interface and the system host. it has built-in packet memory for receive and transmit functions called txq (transmit queue) and rxq (rec eive queue). each queue contains 4kb of memory for back-to-back, non-blocking frame transfer performance. it provides a group of control registers for system control, frame status registers for current packet transmit/receive status, and inter rupts to inform the host of the real time tx/rx status. transmit queue (txq) frame format the frame format for the transmit queue is shown in the following table 3. the first word contains the control information for the frame to transmit. the second word is used to specify the total number of bytes of the frame. the packet data follows. the packet data area holds the frame itself. it may or may not include the crc checksum depending on whether hardware crc checksum generation is enabled. multiple frames can be pipelined in both the transmit queue and receive queue as long as there is enough queue m emory, thus avoiding overrun. for each transmitted frame, the transmit status information for the frame is located in the txsr register. packet memory address offset bit 15 bit 0 2 nd byte 1 st byte 0 control word 2 byte count 4 - up packet data (maximum size is 1916) table 3: transmit queue frame format since multiple packets can be pipelined into the tx packet memory for transmit, the transmit status reflects the s tatus of the packet that is currently being transferred on the mac interface (which may or may not be the last queued packet in the tx queue). the transmit control word is the first 16-bit word in the tx packet memory, followed by a 16-bit byte c ount. it must be word aligned. each control word corresponds to one tx packet. table 4 gives the transmit control word bi t fields. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 42 m9999-102207-1.9 bit description 15 txic transmit interrupt on completion when bit is set, the ksz8842m sets the transmit interrupt after the present frame has been transmitted. 14-10 reserved 9-8 txdpn transmit destination port number when bit is set, this field indicates the destination port(s) where the packet is forwarded from host system. set bit 8 to indicate that port 1 is the destination port. set bit 9 to indicate that port 2 is the destination port. setting all ports to 1 causes the switch engine to broadcast the packet to both ports. setting all bits to 0 has no effect. the internal switch engine forwards the packets according to the switching algorithm in its mac lookup table. 7-6 reserved 5-0 txfid transmit frame id this field specifies the frame id that is used to identify the frame and its associated status information in the transmit status register txsr[5:0]. table 4. transmit control word bit fields the transmit byte count specifies the total number of bytes to be transmitted from the txq. its format is given in t able 5. bit description 15-11 reserved 10-0 txbc transmit byte count transmit byte count. hardware uses the byte count information to conserve the tx buffer memory for better utilization of the packet memory. note: the hardware behavior is unknown if an incorrect byte count information is written to this field. writing a 0 value to this field is not permitted. table 5. transmit byte count format the data area contains six bytes of destination address (da) followed by six bytes of source address (sa), followed by a variable-length number of bytes. on transmit, all bytes are provided by the cpu, including the source address. the ksz8842m does not insert its own source address. the 802.3 frame length word (frame type in etherne t) is not interpreted by the ksz8842m. it is treated transparently as data for transmit operations. receive queue (rxq) frame format the frame format for the receive queue is shown in table 6. the first word contains the status infor mation for the frame received. the second word is the total number of bytes of the rx frame. following that is the packet data area. th e packet data area holds the frame itself. it may or may not include the crc checksum depen ding upon whet her hardware crc stripping is enabled. packet memory address offset bit 15 bit 0 2 nd byte 1 st byte 0 status word 2 byte count 4 - up packet data (maximum size is 1916) table 6. receive queue frame format for receive, the packet receive status always reflects the receive status of the packet received in the current rx packet memory (see table 7). the rxsr register indicates the status of the current received fra me. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 43 m9999-102207-1.9 bit description 15 rxfv receive frame valid when bit is set, indicates that the present frame in the receive packet memory is valid and received from mac/phy. the status information currently in this location is also valid. when bit is reset, indicates that there is either no pending receive frame or current frame is still in the process of receiving and has not completed yet. 14-10 reserved 9-8 rxspn receive source port number when bit is set, this field indicates the source port where the packet was received. (setting bit 9 = 0 and bit 8 = 1 indicates the packet was received from port 1. setting bit 9 = 1 and bit 8 = 0 indicates that the packet was received from por t 2. valid port is either port 1 or port 2. 7 rxbf receive broadcast frame when bit is set, indicates that this frame has a broadcast address. 6 rxmf receive multicast frame when bit is set, it indicates that this frame has a multicast address (including the broadcast address). 5 rxuf receive unicast frame when bit is set, indicates that this frame has a unicast address. 4 reserved 3 rxft receive frame type when bit is set, indicates that the frame is an ethernet-type frame (frame length is greater than 1500 bytes). when clear, indicate that the frame is an ieee 802.3 frame. this bit is not valid for runt frames. 2 rxtl receive frame too long when bit is set, indicates that the frame length exceeds the maximum size of 1518 bytes. frames too long are passed to the host only if the pass bad frame bit is set. note: frame too long is only a frame length indication and does not cause any frame truncation. 1 rxrf receive runt frame when bit is set, indicates that a frame was damaged by a collision or premature termination before the collision window has passed. runt frames are passed to the host only if the pass bad frame bit is set. 0 rxce receive crc error when bit is set, indicates that a crc error has occurred on the current received frame. crc error frame are passed to the host only if the pass bad frame bit is set. table 7. frxq packet receive status table 8 gives the format of the rx byte count field. bit description 15-11 reserved 10-0 rxbc receive byte count receive byte count. table 8. frxq rx byte count field downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 44 m9999-102207-1.9 advanced switch functions spanning tree support to support spanning tree, the host port is the designated port for the processor. the other ports can be configured in one of the five spanning tree states via transmit enable, receive enable and learning disable register settings in registers p1cr2 and p2cr2 for ports 1 and 2, respectively. table 9 shows the port setting and software actions taken for each of the five spanning tree states. disable state port setting software action the port should not forward or receive any packets. learning is disabled. transmit enable = 0, receive enable = 0, learning disable =1 the processor should not send any packets to the port. the switch may still send specific packets to the processor (packets that match some entries in the static mac table with overriding bit set) and the processor should discard those packets. address learning is disabled on the port in this state. blocking state port setting software action only packets to the processor are forwarded. transmit enable = 0, receive enable = 0, learning disable =1 the processor should not send any packets to the port(s) in this state. the processor should program the static mac table with the entries that it needs to receive (for example, bpdu packets). the overriding bit should also be set so that the switch will forward those specific packets to the processor. address learning is disabled on the port in this state. listening state port setting software action only packets to and from the processor are forwarded. learning is disabled. transmit enable = 0, receive enable = 0, learning disable =1 the processor should program the static mac table with the entries that it needs to receive (for example, bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state. address learning is disabled on the port in this state. learning state port setting software action only packets to and from the processor are forwarded. learning is enabled. transmit enable = 0, receive enable = 0, learning disable = 0 the processor should program the static mac table with the entries that it needs to receive (for example, bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state. address learning is enabled on the port in this state. forwarding state port setting software action packets are forwarded and received normally. learning is enabled. transmit enable = 1, receive enable = 1, learning disable = 0 the processor programs the static mac table with the entries that it needs to receive (for example, bpdu packets). the overriding bit is set so that the switch forwards those specific packets to the processor. the processor can send packets to the port(s) in this state. address learning is enabled on the port in this state. table 9. spanning tree states downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 45 m9999-102207-1.9 igmp support for internet group management protocol (igmp) support in layer 2, the ksz8842m provides two components: igmp snooping the ksz8842m traps igmp packets and forwards them only to the processor (host port). the igmp packets are identified as ip packets (either ethernet ip packets, or ieee 802.3 snap ip packets) with ip version = 0x 4 and protocol version number = 0x2. multicast address insertion in the static mac table once the multicast address is programmed in the static mac table, the multicast session is trimmed to the subscribed ports, instead of broadcasting to all ports. ipv6 mld snooping the ksz8842m traps ipv6 multicast listener discovery (mld) packets and forwards them only to the processor (host port). mld snooping is controlled by sgcr2[13] (mld snooping enable) and sgcr2[12] (mld option). setting sgcr2[13] causes the ksz8842m to trap packets that meet all of the following conditions: ? ipv6 multicast packets ? hop count limit = 1 ? ipv6 next header = 1 or 58 (or = 0 with hop-by-hop next header = 1 or 58) ? if sgcr2[12] = 1, ipv6 next header = 43, 44, 50, 51, or 60 (or =0 with hop-by-hop next header = 43, 44, 50, 51, or 60) port mirroring support ksz8842m supports port mirroring comprehensively as: receive only mirror on a port all the packets received on the port are mirrored on the sniffer port. for example, port 1 is pro grammed to be receive sniff and the host port is programmed to be the sniffer port. a packet received on port 1 is destined to port 2 after the internal lookup. the ksz8842m forwards the packet to both port 2 and the host port. the ksz8842m can optionally even forward bad received packets to the sniffer port. transmit only mirror on a port all the packets transmitted on the port are mirrored on the sniffer port. for example, port 1 is programmed to be transmit sniff and the host port is programmed to be the sniffer port. a packet received on port 2 is destined to port 1 after the internal lookup. the ksz8842m forwards the packet to both port 1 and the host port. receive and transmit mirror on two ports all the packets received on port a and transmitted on port b are mirrored on the sniffer port. to turn on the and feature, set register sgcr2, bit 8 to 1. for example, port 1 is programmed to be receive sniff, port 2 is programmed to be transmit sniff, and the host port is programmed to be the sniffer port. a packet received on port 1 is destined to port 2 after the internal lookup. the ksz8842m forwards the packet to both port 2 and the host port. multiple ports can be selected as receive sniff or transmit sniff. in addition, any port can be s elected as the sniffer port. all these per port features can be selected through registers p1cr2, p2cr2, and p3cr2 for ports 1, 2, and the host port, respectively. ieee 802.1q vlan support the ksz8842m supports 16 active vlans out of the 4096 possible vlans specified in the ieee 802.1q specification. ksz8842m provides a 16-entry vlan table, which converts the 12-bits vlan id (vid) to the 4-bits filter id (fid) for address lookup. if a non-tagged or null-vid-tagged packet is received, the ingress port default vid is used for lookup. in vlan mode, the lookup process starts with vlan table lookup to determine whether the vid is valid. if the vid is not valid, the packet is dropped and its address is not learned. if the vid is valid, the fid is retrieved for further lookup. the fid + destination address (fid+da) are used to determine the destination port. the fid + source address (fid+sa) are used for address learning. (see tables 10 and 11.) downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 46 m9999-102207-1.9 da found in static mac table? use fid flag? fid match? da+fid found in dynamic mac table? action no dont care dont care no broadcast to the membership ports defined in the vlan table bits [18:16] no dont care dont care yes send to the destination port defined in the dynamic mac address table bits [53:52] yes 0 dont care dont care send to the destination port(s) defined in the static mac address table bits [50:48] yes 1 no no broadcast to the membership ports defined in the vlan table bits [18:16] yes 1 no yes send to the destination port defined in the dynamic mac address table bits [53:52] yes 1 yes dont care send to the destination port(s) defined in the static mac address table bits [50:48] table 10. fid+da lookup in vlan mode fid+sa found in dynamic mac table? action no learn and add fid+sa to the dynamic mac address table yes update time stamp table 11. fid+sa lookup in vlan mode qos priority support the ksz8842m provides quality of service (qos) for applications such as voip and video co nferencing. offering four priority queues per port, the per-port transmit queue can be split into four priority queues: queue 3 is the highest priority queue and queue 0 is the lowest priority queue. bit 0 of registers p1cr1, p2cr1, and p3cr1 is used to enable split transmit queues for ports 1, 2, and the host port, respectively. port-based priority with port-based priority, each ingress port is individually classified as a high-priority rece iving port. all packets received at the high-priority receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split. bit 4 and 3 of registers p1cr1, p2cr1, and p3cr1 is used to enable port-based priority for ports 1, 2, and the host port, respectively. 802.1p-based priority for 802.1p-based priority, the ksz8842m examines the ingress (incoming) packets to determine whether they are tagged. if tagged, the 3-bit priority field in the vlan tag is retrieved and compared against the priority mapping va lue, as specified by the register sgcr6. the priority mapping value is programmable. figure 14 illustrates how the 802.1p priority field is embedded in the 802.1q vlan tag. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 47 m9999-102207-1.9 tci 76 6 2 length data fcs 2 46-1500 4 tagged packet type (8100 for ethernet) 802.1 p vlan id bytes bits 16 3 12 802.1q vlan tag 2 sa vpid preamble da 1 cfi 1 sfd figure 14. 802.1p priority field format 802.1p based priority is enabled by bit 5 of registers p1cr1, p2cr1, and p3cr1 for ports 1, 2, and the host por t, respectively. the ksz8842m provides the option to insert or remove the priority tagged frame's header at each individu al egress port. this header, consisting of the 2 bytes vlan protocol id (vpid) and the 2 bytes tag control info rmation field (tci), is also referred to as the 802.1q vlan tag. tag insertion is enabled by bit 2 of registers p1cr1, p2cr1, and p3cr1 for ports 1, 2, and the host port, respectively. at the egress port, untagged packets are tagged with the ingress ports default tag. the default tags are programmed in register sets p1vidcr, p2vidcr, and p3vidcr for ports 1, 2 and the host port, respectively. the ksz8842m does not add tags to already tagged packets. tag removal is enabled by bit 1 of registers p1cr1, p2cr1, and p3cr1 for ports 1, 2, and the host port, respectively. at the egress port, tagged packets will have their 802.1q vlan tags removed. the ksz8842m will not modify untagged packets. the crc is recalculated for both tag insertion and tag removal. 802.1p priority field re-mapping is a qos feature that allows the ksz8842m to set the user priority ceiling at any ingress port. if the ingress packets priority field has a higher priority value than the default tags priority fie ld of the i ngress port, the packets priority field is replaced with the default tags priority field. the user priority ceiling is enabled by bit 3 of registers p1cr2, p2cr2, and p3cr2 for ports 1, 2, and the host port, respectively. diffserv based priority diffserv-based priority uses the tos registers shown in the priority control registers section. the t os priority control registers implement a fully decoded, 128-bit differentiated services code point (dscp) register to determine packet priority from the 6-bit tos field in the ip header. when the most significant 6 bits of the tos field are f ully decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the dscp register to determine prio rity. rate limiting support the ksz8842m supports hardware rate limiting from 64 kbps to 88 mbps, independently on the receive si de and on the transmit side on a per port basis. for 10-base t, a rate setting above 10 mbps means the rate is not li mited. on the receive side, the data receive rate for each priority at each port can be limited by setting up ingress rate control registers. on the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up egress rate control registers. the size of each frame has options to include minimum ifg (inter frame gap) or preamble byte, in addition to the data field (from packet da to fcs). for ingress rate limiting, ksz8842m provides options to selectively choose frames from all types, multicast, br oadcast, and flooded unicast frames. the ksz8842m counts the data rate from those selected type of frames. packets are dropped at the ingress port when the data rate exceeds the specified rate limit. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 48 m9999-102207-1.9 for egress rate limiting, the leaky bucket algorithm is applied to each output priority queue for shaping output traffic. inter frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. the throughput of each output priority queue is limited by the egress rate specified. if any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. after the memory of the queue or the port is used up, packet dropping or flow control will be triggered. as a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress end, and may be therefore slightly less than the specified egress rate. to reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth. mac filtering function use the static table to assign a dedicated mac address to a specific port. when a unicast mac address is not recorded in the static table, it is also not learned in the dynamic mac table. the ksz8842m includes an option that can filter or forward unicast packets for an unknown mac address. this option is enabled by sgcr7[7]. the unicast mac address filtering function is useful in preventing the broadcast of unicast packets that could degrade the quality of this port in applications such as voice over internet protocol (voip). configuration interface the ksz8842m operates only as a managed switch. eeprom interface it is optional in the ksz8842m to use an external eeprom. in the case that an eeprom is not used, the eeen pin must be tied low or floating. the external serial eeprom with a standard microwire bus interface is used for non-volatile storage of information such as the host mac address, base address, and default configuration settings. the ksz8842m can detect if the eeprom is a 1kb (93c46) or 4kb (93c66) eeprom device (the 93c46 and the 93c66 are typical eeprom devices). the eeprom is organized as 16-bit mode. if the eeen pin is pulled high, the ksz8842m performs an automatic read of the external eeprom words 0h to 6h after the de-assertion of reset. the eeprom values are placed in certain host-accessible registers. eepro m read/write functions can also be performed by software read/writes to the eepcr registers. the ksz8842m eeprom format is given below. word 15 8 7 0 0h base address 1h host mac address byte 2 host mac address byte 1 2h host mac address byte 4 host mac address byte 3 3h host mac address byte 6 host mac address byte 5 4h reserved 5h reserved 6h configparam (see table 13) 7h-3fh not used for ksz8842m (available for user to use) table 12. eeprom format downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 49 m9999-102207-1.9 the format for configparam is shown in table 13. bit bit name description 15 -2 reserved reserved 1 clock_rate internal clock rate selection 0: 125 mhz 1: 25 mhz note: at power up, this chip operates on 125 mhz clock. the internal frequency can be dropped to 25 mhz via the external eeprom. 0 asyn_8bit async 8-bit or 16-bit bus select 1= bus is configured for 16-bit width 0= bus is configured for 8-bit width (32-bit width, ksz8842-32, dont care this bit setting) table 13. configparam word in eeprom format loopback support the ksz8842m provides loopback support for remote diagnostic of failure. in loopback mode, the speed at both phy ports will be set to 100base-tx full-duplex mode. two types of loopback are supported: far-end loopback and near-end (remote) loopback. far-end loopback far-end loopback is conducted between the ksz8842ms two phy ports. the loopback path starts at the originating. phy ports receive inputs (rxp/rxm), wraps around at the loopback phy ports pmd/pma, and ends at the originating phy ports transmit outputs (txp/txm). bit [8] of registers p1cr4 and p2cr4 is used to enable far-end loopback for ports 1 and 2, respectively. alternatively, bi t [14] of registers p1mbcr and p2mbcr can also be used to enable far-end loopback. the port 2 far-end loo pback path is illustrated in the figure 15. near-end (remote) loopback near-end (remote) loopback is conducted at either phy port 1 or phy port 2 of the ksz8842m. the loopback path starts at the phy ports receive inputs (rxpx/rxmx), wraps around at the same phy ports pmd/pma, and ends at the phy ports transmit outputs (txpx/txmx). bit [1] of registers p1phyctrl and p2phyctrl is used to enable near-end loopback for ports 1 and 2, respectively. alternatively, bit [9] of registers p1scslmd and p2scslmd can also be used to enable near-end loopback. the both ports 1 and 2 near-end loopback paths are illustrated in the following figure 16. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 50 m9999-102207-1.9 pm d2/pm a2 pcs2 m ac2 sw itch m ac1 pc s1 pm d1/pm a 1 o r ig in a tin g ph y port 1 ph y port 2 f ar-en d l oop b ack rxp1 / rxm 1 txp1 / txm 1 figure 15. port 2 far-end loopback path pm d2/pm a2 pcs2 mac2 switch mac1 pcs1 pm d1/pm a1 rx p 1 / rx m 1 t xp1 / tx m 1 t xp2 / tx m 2 rx p 2 / rx m 2 ph y po r t 2 n e a r - e nd ( r em ot e ) l oopb ac k ph y po r t 1 n ear - end ( r em ot e ) lo opba c k figure 16. port 1 and port 2 near-end (remote) loopback path downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 51 m9999-102207-1.9 cpu interface i/o registers the ksz8842m provides an eisa-like, isa-like, or vlbus-like bus interface for the cpu to access its internal i/o registers. i/o registers serve as the address that the microprocessor uses when communicating with the device. this is used for configuring operational settings, reading or writing control, status information, and transferring packets by reading and writing through the packet data registers. i/o registers input/output (i/o) registers are limited to 16 locations as required by most isa bus-based systems; therefore, regist ers are assigned to different banks. the last word of the i/o register locations (0xe - 0xf) is shared by all banks and can be used to change the bank in use. the following i/o space mapping tables apply to 8, 16 or 32-bit bus products. depending upon the bus interface used and byte enable signals (be[3:0]n control byte access), each i/o access can be performed as an 8-bit, 16-bit, or 32-bit operation. (the ksz8842m is not limited to 8/16-bit performance and 32-bit read/write are also supported). downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 52 m9999-102207-1.9 internal i/o space mapping i/o register location bank location 32-bit 16-bit 8-bit bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 0x0 base address [7:0] host mac address low [7:0] on-chip bus control [7:0] 0x0 - 0x1 0x1 base address [15:8] reserved host mac address low [15:8] on-chip bus control [15:8] reserved 0x2 host mac address mid [7:0] eeprom control [7:0] 0x0 to 0x3 0x2 - 0x3 0x3 reserved reserved host mac address mid [15:8] eeprom control [15:8] reserved 0x4 qmu rx flow control watermark [7:0] host mac address high [7:0] memory bist info [7:0] 0x4 - 0x5 0x5 qmu rx flow control watermark [15:8] reserved host mac address high [15:8] memory bist info [15:8] reserved 0x6 bus error status [7:0] global reset [7:0] 0x4 to 0x7 0x6 - 0x7 0x7 bus error status [15:8] reserved reserved global reset [15:8] reserved 0x8 bus burst length [7:0] bus configuration [7:0] 0x8 - 0x9 0x9 bus burst length [15:8] reserved reserved bus configuration [15:8] reserved 0xa 0x8 to 0xb 0xa - 0xb 0xb reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8] downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 53 m9999-102207-1.9 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 bank 15 0x0 0x0 - 0x1 0x1 reserved 0x2 0x0 to 0x3 0x2 - 0x3 0x3 reserved 0x4 0x4 - 0x5 0x5 reserved 0x6 0x4 to 0x7 0x6 - 0x7 0x7 reserved 0x8 0x8 - 0x9 0x9 reserved 0xa 0x8 to 0xb 0xa - 0xb 0xb reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8] downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 54 m9999-102207-1.9 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 16 bank 17 bank 18 bank 19 bank 20 bank 21 bank 22 bank 23 0x0 transmit control [7:0] txq command [7:0] interrupt enable [7:0] multicast table 0 [7:0] 0x0 - 0x1 0x1 transmit control [15:8] txq command [15:8] interrupt enable [15:8] multicast table 0 [15:8] reserved 0x2 transmit status [7:0] rxq command [7:0] interrupt status [7:0] multicast table 1 [7:0] 0x0 to 0x3 0x2 - 0x3 0x3 transmit status [15:8] rxq command [15:8] interrupt status [15:8] multicast table 1 [15:8] reserved 0x4 receive control [7:0] tx frame data pointer [7:0] receive status [7:0] multicast table 2 [7:0] 0x4 - 0x5 0x5 receive control [15:8] tx frame data pointer [15:8] receive status [15:8] multicast table 2 [15:8] reserved 0x6 rx frame data pointer [7:0] receive byte counter [7:0] multicast table 3 [7:0] 0x4 to 0x7 0x6 - 0x7 0x7 reserved rx frame data pointer [15:8] receive byte counter [15:8] multicast table 3 [15:8] reserved 0x8 txq memory information [7:0] qmu data low [7:0] 0x8 - 0x9 0x9 txq memory information [15:8] qmu data low [15:8] reserved reserved reserved 0xa rxq memory information [7:0] qmu data high [7:0] 0x8 to 0xb 0xa - 0xb 0xb rxq memory information [15:8] qmu data high [15:8] reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8] downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 55 m9999-102207-1.9 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 24 bank 25 bank 26 bank 27 bank 28 bank 29 bank 30 bank 31 0x0 0x0 - 0x1 0x1 reserved 0x2 0x0 to 0x3 0x2 - 0x3 0x3 reserved 0x4 0x4 - 0x5 0x5 reserved 0x6 0x4 to 0x7 0x6 - 0x7 0x7 reserved 0x8 0x8 - 0x9 0x9 reserved 0xa 0x8 to 0xb 0xa - 0xb 0xb reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8] downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 56 m9999-102207-1.9 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 32 bank 33 bank 34 bank 35 bank 36 bank 37 bank 38 bank 39 0x0 switch id and enable [7:0] switch global control 6 [7:0] mac address 1 [7:0] 0x0 - 0x1 0x1 switch id and enable [15:8] switch global control 6 [15:8] reserved mac address 1 [15:8] 0x2 switch global control 1 [7:0] switch global control 7 [7:0] mac address 2 [7:0] 0x0 to 0x3 0x2 - 0x3 0x3 switch global control 1 [15:8] switch global control 7 [15:8] reserved mac address 2 [15:8] 0x4 switch global control 2 [7:0] mac address 3 [7:0] 0x4 - 0x5 0x5 switch global control 2 [15:8] reserved mac address 3 [15:8] 0x6 switch global control 3 [7:0] 0x4 to 0x7 0x6 - 0x7 0x7 switch global control 3 [15:8] reserved 0x8 switch global control 4 [7:0] 0x8 - 0x9 0x9 switch global control 4 [15:8] reserved 0xa switch global control 5 [7:0] 0x8 to 0xb 0xa - 0xb 0xb switch global control 5 [15:8] reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8] downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 57 m9999-102207-1.9 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 40 bank 41 bank 42 bank 43 bank 44 bank 45 bank 46 bank 47 0x0 tos priority control 1 [7:0] tos priority control 7 [7:0] indirect access ctrl. [7:0] digital test status [7:0] phy1 mii- register basic control [7:0] phy2 mii- register basic control [7:0] phy1 linkmd control/status [7:0] 0x0 - 0x1 0x1 tos priority control 1 [15:8] tos priority control 7 [15:8] indirect access ctrl. [15:8] reserved digital test status [15:8] phy1 mii- register basic control [15:8] phy2 mii- register basic control [15:8] phy1 linkmd control/status [15:8] 0x2 tos priority control 2 [7:0] tos priority control 8 [7:0] indirect access data 1 [7:0] analog test status [7:0] phy1 mii- register basic status [7:0] phy2 mii- register basic status [7:0] phy1 special control/status [7:0] 0x0 to 0x3 0x2 - 0x3 0x3 tos priority control 2 [15:8] tos priority control 8 [15:8] indirect access data 1 [15:8] reserved analog test status [15:8] phy1 mii- register basic status [15:8] phy2 mii- register basic status [15:8] phy1 special control/status [15:8] 0x4 tos priority control 3 [7:0] indirect access data 2 [7:0] digital test control [7:0] phy1 phyid low [7:0] phy2 phyid low [7:0] phy2 linkmd control/status [7:0] 0x4 - 0x5 0x5 tos priority control 3 [15:8] reserved indirect access data 2 [15:8] reserved digital test control [15:8] phy1 phyid low [15:8] phy2 phyid low [15:8] phy2 linkmd control/status [15:8] 0x6 tos priority control 4 [7:0] indirect access data 3 [7:0] analog test control 0 [7:0] phy1 phyid high [7:0] phy2 phyid high [7:0] phy2 special control/status [7:0] 0x4 to 0x7 0x6 - 0x7 0x7 tos priority control 4 [15:8] reserved indirect access data 3 [15:8] reserved analog test control 0 [15:8] phy1 phyid high [15:8] phy2 phyid high [15:8] phy2 special control/status [15:8] 0x8 tos priority control 5 [7:0] indirect access data 4 [7:0] analog test control 1 [7:0] phy1 a.n. advertisement [7:0] phy2 a.n. advertisement [7:0] 0x8 - 0x9 0x9 tos priority control 5 [15:8] reserved indirect access data 4 [15:8] reserved analog test control 1 [15:8] phy1 a.n. advertisement [15:8] phy2 a.n. advertisement [15:8] reserved 0xa tos priority control 6 [7:0] indirect access data 5 [7:0] analog test control 2 [7:0] phy1 a.n. link partner ability [7:0] phy2 a.n. link partner ability [7:0] 0x8 to 0xb 0xa - 0xb 0xb tos priority control 6 [15:8] reserved indirect access data 5 [15:8] reserved analog test control 2 [15:8] phy1 a.n. link partner ability [15:8] phy2 a.n. link partner ability [15:8] reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8] downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 58 m9999-102207-1.9 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 48 bank 49 bank 50 bank 51 bank 52 bank 53 bank 54 bank 55 0x0 port 1 control 1 [7:0] port 1 phy special control/status, linkmd [7:0] port 2 control 1 [7:0] port 2 phy special control/status, linkmd [7:0] host port control 1 [7:0] 0x0 - 0x1 0x1 port 1 control 1 [15:8] port 1 phy special control/status, linkmd [15:8] port 2 control 1 [15:8] port 1 phy special control/status, linkmd [15:8] host port control 1 [15:8] reserved 0x2 port 1 control 2 [7:0] port 1 control 4 [7:0] port 2 control 2 [7:0] port 2 control 4 [7:0] host port control 2 [7:0] 0x0 to 0x3 0x2 - 0x3 0x3 port 1 control 2 [15:8] port 1 control 4 [15:8] port 2 control 2 [15:8] port 2 control 4 [15:8] host port control 2 [15:8] reserved 0x4 port 1 vid control [7:0] port 1 status [7:0] port 2 vid control [7:0] port 2 status [7:0] host port vid control [7:0] 0x4 - 0x5 0x5 port 1 vid control [15:8] port 1 status [15:8] port 2 vid control [15:8] port 2 status [15:8] host port vid control [15:8] reserved 0x6 port 1 control 3 [7:0] port 2 control 3 [7:0] host port control 3 [7:0] 0x4 to 0x7 0x6 - 0x7 0x7 port 1 control 3 [15:8] reserved port 2 control 3 [15:8] reserved host port control 3 [15:8] reserved 0x8 port1 ingress rate control [7:0] port2 ingress rate control [7:0] host port ingress rate control [7:0] 0x8 - 0x9 0x9 port1 ingress rate control [15:8] reserved port2 ingress rate control [15:8] reserved host port ingress rate control [15:8] reserved 0xa port1 egress rate control [7:0] port2 egress rate control [7:0] host port egress rate control [7:0] 0x8 to 0xb 0xa - 0xb 0xb port1 egress rate control [15:8] reserved port2 egress rate control [15:8] reserved host port egress rate control [15:8] reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8] downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 59 m9999-102207-1.9 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 56 bank 57 bank 58 bank 59 bank 60 bank 61 bank 62 bank 63 0x0 0x0 - 0x1 0x1 reserved 0x2 0x0 to 0x3 0x2 - 0x3 0x3 reserved 0x4 0x4 - 0x5 0x5 reserved 0x6 0x4 to 0x7 0x6 - 0x7 0x7 reserved 0x8 0x8 - 0x9 0x9 reserved 0xa 0x8 to 0xb 0xa - 0xb 0xb reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8] downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 60 m9999-102207-1.9 register map: switch & mac/phy do not write to bit values or to registers defined as reserved. manipulating reserved bits or registers caus es unpredictable and often fatal results. if the user wants to write to these reserved bits, the user has to read back these reserved bits (ro or rw) first, then or with the read value of the reserved bits and write back to these res erved bits. bit type definition ro = read only. rw = read/write. w1c = write 1 to clear (writing a one to this bit clears it). bank 0-63 bank select register (0x0e): bsr (same location in all banks) the bank select register is used to select or to switch between different sets of register banks for i/o access. there are a total of 64 banks available to select, including the built-in switch engine registers. bit default value r/w description 15-6 0x000 ro reserved 5-0 0x00 r/w bsa bank select address bits bsa bits select the i/o register bank in use. this register is always accessible regardless of the register bank currently selected. notes: the bank select register can be accessed as a doubleword (32-bit) at offset 0xc, as a word (16-bit) at offset 0xe, or as a byte (8-bit) at offset 0xe. a doubleword write to offset 0xc writes to the bank select register but does not write to registers 0xc and 0xd; it only writes to register 0xe. bank 0 base address register (0x00): bar this register holds the base address for decoding a device access. its value is loaded from the extern al eeprom (0x0h) upon a power-on reset if the eeprom enable (eeen) pin is tied to high. its value can also be modified after reset. writing to this register does not store the value into the eeprom. when the eeen pin is tied to low, the default base address is 0x0300. bit default value r/w description 15-8 0x03 if eeen is low or, the value from eeprom if eeen is high rw barh base address high these bits are compared against the address on the bus addr[15:8] to determine the base for the ksz8842m registers. 7-5 0x0 if eeen is low or, the value from eeprom if eeen is high rw barl base address low these bits are compared against the address on the bus addr[7:5] to determine the base for the ksz8842m registers. 4-0 0x00 ro reserved downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 61 m9999-102207-1.9 bank 0 qmu rx flow control high watermark configuration register (0x04): qrfcr this register contains the user defined qmu rx queue high watermark configuration bit as below. bit default value r/w description 15-13 0x0 ro reserved 12 0 rw qmu rx flow control high watermark configuration 0: 3 kbytes 1: 2 kbytes 11-0 0x000 ro reserved bank 0 bus error status register (0x06): besr this register flags the different kinds of errors on the host bus. bit default value r/w description 15 0 ro ibec illegal byte enable combination 1: illegal byte enable combination occurs. the illegal combination value can be found from bit 14 to bit 11. 0: legal byte enable combination. write 1 to clear. 14-11 - ro ibecv illegal byte enable combination value bit 14: byte enable 3. bit 13: byte enable 2. bit 12: byte enable 1. bit 11: byte enable 0. this value is valid only when bit 15 is set to 1. 10 0 ro ssaxfer simultaneous synchronous and asnychronous transfers 1: synchronous and asnychronous transfers occur simultaneously. 0: normal. write 1 to clear. 9-0 0x000 ro reserved bank 0 bus burst length register (0x08): bblr before the burst can be sent, the burst length needs to be programmed. bit default value r/w description 15 0 ro reserved 14-12 0x0 rw brl burst length (for burst read and write) 000: single. 011: fixed burst read length of 4. 101: fixed burst read length of 8. 111: fixed burst read length of 16. 11-0 0x000 ro reserved downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 62 m9999-102207-1.9 bank 1: reserved except bank select register (0xe). bank 2 host mac address register low (0x00): marl this register along with the other two host mac address registers are loaded starting at word loc ation 0x1 of the eeprom upon hardware reset. the software driver can modify the register, but it will not modify the orig inal host mac address value in the eeprom. these six bytes of host mac address in external eeprom are loaded to these t hree registers as mapping below: marl[15:0] = eeprom 0x1(mac byte 2 and 1) marm[15:0] = eeprom 0x2(mac byte 4 and 3) marh[15:0] = eeprom 0x3(mac byte 6 and 5) the host mac address is used to define the individual destination address that the ksz8842m responds to when receiving frames. network addresses are generally expressed in the form of 01:23:45:67:89:ab, where the bytes are received from left to right, and the bits within each byte are received from right to left (lsb to msb). f or example, the actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101. these three registers value for host mac address 01:23:45:67:89:ab will be held as below: marl[15:0] = 0x89ab marm[15:0] = 0x4567 marh[15:0] = 0x0123 the following table shows the register bit fields. bit default value r/w description 15-0 - rw marl mac address low the least significant word of the mac address. bank 2 host mac address register middle (0x02): marm the middle word of host mac address. the following table shows the register bit fields. bit default value r/w description 15-0 - rw marm mac address middle the middle word of the mac address. bank 2 host mac address register high (0x04): marh the high word of host mac address. the following table shows the register bit fields. bit default value r/w description 15-0 - rw marh mac address high the most significant word of the mac address. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 63 m9999-102207-1.9 bank 3 on-chip bus control register (0x00): obcr this register controls the on-chip bus speed for the ksz8842m. it is used for power management when the external host cpu is running at a slow frequency. the default of the on-chip bus speed is 125 mhz without eeprom. when the external host cpu is running at a higher clock rate, the on-chip bus should be adjusted for the best performance. bit default value r/w description 15-2 - ro reserved 1-0 0x0 rw obsc on-chip bus speed control 00: 125mhz. 01: 62.5mhz. 10: 41.66mhz. 11: 25mhz. note: when external eeprom is enabled, the bit 1 in configparm word (0x6h) is used to contol this speed as below: bit 1 = 0 , this value will be 00 for 125 mhz. bit 1 = 1 , this value will be 11 for 25 mhz. (user still can write these two bits to change speed after eeprom data loaded) bank 3 eeprom control register (0x02): eepcr to support an external eeprom, tie the eeprom enable (eeen) pin to high; otherwise, tie it to low. if an external eeprom is not used, the default chip base address (0x300), and the software programs the host mac address. if an eeprom is used in the design (eeprom enable pin to high), the chip base address and host mac address ar e loaded from the eeprom immediately after reset. the ksz8842m allows the software to access (read and write) the eeprom directly; that is, the eeprom access timing can be fully controlled by the software if the eeprom softwar e access bit is set. bit default value r/w description 15-5 - ro reserved 4 0 rw eesa eeprom software access 1: enable software to access eeprom through bit 3 to bit 0. 0: disable software to access eeprom. 3 - ro eecb eeprom status bit data receive from eeprom. this bit directly reads the eedi pin. 2-0 0x0 rw eecb eeprom control bits bit 2: data transmit to eeprom. this bit directly controls the devices eedo pin. bit 1: serial clock. this bit directly controls the devices eesk pin. bit 0: chip select for eeprom. this bit directly controls the devices eecs pin. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 64 m9999-102207-1.9 bank 3 memory bist info register (0x04): mbir bit default value r/w description 15-13 0x0 ro reserved 12 - ro txmbf tx memory bist finish when set, it indicates the memory built in self test completion for the tx memory. 11 - ro txmbfa tx memory bist fail when set, it indicates the memory built in self test has failed. 10-5 - ro reserved 4 - ro rxmbf rx memory bist finish when set, it indicates the memory built in self test completion for the rx memory. 3 - ro rxmbfa rx memory bist fail when set, it indicates the memory built in self test has failed. 2-0 - ro reserved bank 3 global reset register (0x06): grr this register controls the global reset function with information programmed by the cpu. bit default value r/w description 15-1 0x0000 ro reserved 0 0 rw global soft reset 1: software reset is active. 0: software reset is inactive. software reset will affect phy, mac, qmu, dma, and the switch core, only the biu (base address registers) remains unaffected by a software reset. bank 3 bus configuration register (0x08): bcfg this register is a read-only register. the bit 0 is automatically downloaded from bit 0 configparm word of eeprom, if pin eeen is high (enabled eeprom) bit default value r/w description 15-1 0x0000 ro reserved 0 - ro bus configuration (only for ksz8842-16 device) 1: bus width is 16 bits. 0: bus width is 8 bits. (this bit is only avaiable when eeprom is enabled) banks 4 C 15: reserved except bank select register (0xe) . downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 65 m9999-102207-1.9 bank 16 transmit control register (0x00): txcr this register holds control information programmed by the cpu to control the qmu transmit module functi on. bit default value r/w description 15 - ro reserved 14 0x0 rw reserved 13 0x0 rw reserved 12-4 - ro reserved 3 0x0 rw txfce transmit flow control enable when this bit is set, the qmu sends flow control pause frames from the host port if the rx fifo has reached its threshold. note: the sgcr3[5] in bank 32 also needs to be enabled. 2 0x0 rw txpe transmit padding enable when this bit is set, the ksz8842m automatically adds a padding field to a packet shorter than 64 bytes. note: setting this bit requires enabling th e add crc feature to avoid crc errors for the transmit packet. 1 0x0 rw txce transmit crc enable when this bit is set, the ksz8842m automatically adds a crc checksum field to the end of a transmit frame. 0 0x0 rw txe transmit enable when this bit is set, the transmit module is enabled and placed in a running state. when reset, the transmit process is placed in the stopped state after the transmission of the current frame is completed. bank 16 transmit status register (0x02): txsr this register keeps the status of the last transmitted frame. bit default value r/w description 15-6 0x000 ro reserved 5-0 - ro txfid transmit frame id this field identifies the transmitted frame. all of the transmit status information in this register belongs to the frame with this id. bank 16 receive control register (0x04): rxcr this register holds control information programmed by the cpu to control the receive function. bit default value r/w description 15-11 - ro reserved 10 0x0 rw rxfce receive flow control enable when this bit is set, the ksz8842m will acknowledge a pause frame from the receive interface; i.e., the outgoing packets are pending in the transmit buffer until the pause frame control timer expires. when this bit is cleared, flow control is not enabled. 9 0x0 rw rxefe receive error frame enable when this bit is set, crc error frames are allowed to be received into the rx q ueue. when reset, all crc error frames are discarded. 8 - ro reserved 7 0x0 rw rxbe receive broadcast enable when this bit is set, the rx module receives all the broadcast frames. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 66 m9999-102207-1.9 bit default value r/w description 6 0x0 rw rxme receive multicast enable when this bit is set, the rx module receives all the multicast frames (including broadcast frames). 5 0x0 rw rxue receive unicast when this bit is set, the rx module receives unicast frames that match the 48-bit station mac address of the module. 4 0x0 rw rxra receive all when this bit is set, the ksz8842m receives all incoming frames, regardless of the frames destination address. 3 0x0 rw rxsce receive strip crc when this bit is set, the ksz8842m strips the crc on the received frames. once cleared, the crc is stored in memory following the packet. 2 0x0 rw qmu receive multicast hash-table enable when this bit is set, this bit enables the rx function to receive multicast frames that pass the crc hash filtering mechanism. 1 - ro reserved 0 0x0 rw rxe receive enable when this bit is set, the rx block is enabled and placed in a running state. when reset, the receive process is placed in the stopped state upon completing reception of the current frame. bank 16 txq memory information register (0x08): txmir this register indicates the amount of free memory available in the txq of the qmu module. bit default value r/w description 15-13 - ro reserved 12-0 - ro txma transmit memory available the amount of memory available is represented in units of byte. the txq memory is used for both frame payload, control word. there is total 4096 bytes in txq. note: software must be written to ensure that there is enough memory for the next transmit frame including control information before transmit data is written to the txq. bank 16 rxq memory information register (0x0a): rxmir this register indicates the amount of receive data available in the rxq of the qmu module. bit default value r/w description 15-13 - ro reserved 12-0 - ro rxma receive packet data available the amount of receive packet data available is represented in units of byte. the rxq memory is used for both frame payload, status word. there is total 4096 bytes in rxq. this counter will update after a complete packet is received and also issues an interrupt when receive interrupt enable ier[13] in bank 18 is set. note: software must be written to empty the rxq memory to allow for the new rx frame. if this is not done, the frame may be discarded as a result of insufficient rxq memory. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 67 m9999-102207-1.9 bank 17 txq command register (0x00): txqcr this register is programmed by the host cpu to issue a transmit command to the txq. the present transmit frame in the txq memory is queued for transmit. bit default value r/w description 15-1 - ro reserved 0 0x0 rw txetf enqueue tx frame when this bit is set as 1, the current tx frame prepared in the tx buffer is queued for transmit. note: this bit is self-clearing after the frame is finished transmitting. the software should wait for the bit to be cleared before setting up another new tx frame. bank 17 rxq command re gister (0x02): rxqcr this register is programmed by the host cpu to issue release command to the rxq. the current frame in the rxq frame buffer is read out by the host and the memory space is released. bit default value r/w description 15-1 - ro reserved do not write to this register. 0 0x0 rw rxrrf release rx frame when this bit is set as 1, the current rx frame buffer is released. note: this bit is self-clearing after the fr ame memory is released. the software should wait for the bit to be cleared before processing new rx frames. bank 17 tx frame data pointer register (0x04): txfdpr the value of this register determines the address to be accessed within the txq frame buffer. when the auto incr ement is set, it will automatically increment the pointer value on write accesses to the data register. the counter is incremented by one for every byte access, by two for every word access, and by four for every double word access. bit default value r/w description 15 - ro reserved 14 0x0 rw txfpai tx frame data pointer auto increment when this bit is set, the tx frame data pointer register increments automatically on accesses to the data register. the increment is by one for every byte access, by two for every word access, and by four for every doubleword access. when this bit is reset, the tx frame data pointer is manually controlled by user to access the tx frame location. 13-11 - ro reserved 10-0 0x0 rw txfp tx frame pointer tx frame pointer index to the frame data register for access. this field reset to next available tx frame location when the tx frame data has been enqueued through the txq command register. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 68 m9999-102207-1.9 bank 17 rx frame data pointer register (0x06): rxfdpr the value of this register determines the address to be accessed within the rxq frame buffer. when the auto increment is set, it will automatically increment the rxq pointer on read accesses to the data register. the counter is incremented is by one for every byte access, by two for every word access, and by four f or every double word access. bit default value r/w description 15 - ro reserved 14 0x0 rw rxfpai rx frame pointer auto increment when this bit is set, the rxq address register increments automatically on accesses to the data register. the increment is by one for every byte access, by two for every word access, and by four for every double word access. when this bit is reset, the rx frame data pointer is manually controlled by user to access the rx frame location. 13-11 - ro reserved 10-0 0x0 rw rxfp rx frame pointer rx frame data pointer index to the data register for access. this field reset to next available rx frame location when rx frame release command is issued (through the rxq command register). bank 17 qmu data register low (0x08): qdrl this register qdrl(0x08-0x09) contains the low data word presently addressed by the pointer register. r eading maps from the rxq, and writing maps to the txq. bit default value r/w description 15-0 - rw qdrl queue data register low this register is mapped into two uni-directional buffers for 16-bit buses, and one uni- directional buffer for 32-bit buses, (txq when write, rxq when read) that allow moving words to and from the ksz8842m regardless of whether the pointer is even, odd, or dword aligned. byte, word, and dword access can be mixed on the fly in any order. this register along with dqrh is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit buses, to facilitate dword move operations. bank 17 qmu data regi ster high (0x0a): qdrh this register qdrh(0x0a-0x0b) contains the high data word presently addressed by the pointer register. reading maps from the rxq, and writing maps to the txq. bit default value r/w description 15-0 - rw qdrl queue data register high this register is mapped into two uni-directional buffers for 16-bit buses, and one uni- directional buffer for 32-bit buses, (txq when write, rxq when read) that allow moving words to and from the ksz8842m regardless of whether the pointer is even, odd, or dword aligned. byte, word, and dword access can be mixed on the fly in any order. this register along with dqrl is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit buses, to facilitate dword move operations. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 69 m9999-102207-1.9 bank 18 interrupt enable register (0x00): ier this register enables the interrupts from the qmu and other sources. bit default value r/w description 15 0x0 rw lcie link change interrupt enable when this bit is set, the link change interrupt is enabled. when this bit is reset, the link change interrupt is disabled. 14 0x0 rw txie transmit interrupt enable when this bit is set, the transmit interrupt is enabled. when this bit is reset, the transmit interrupt is disabled. 13 0x0 rw rxie receive interrupt enable when this bit is set, the receive interrupt is enabled. when this bit is reset, the receive interrupt is disabled. 12 0x0 rw reserved 11 0x0 rw rxoie receive overrun interrupt enable when this bit is set, the receive overrun interrupt is enabled. when this bit is reset, the receive overrun interrupt is disabled. 10 0x0 rw reserved 9 0x0 rw txpsie transmit process stopped interrupt enable when this bit is set, the transmit process stopped interrupt is enabled. when this bit is reset, the transmit process stopped interrupt is disabled. 8 0x0 rw rxpsie receive process stopped interrupt enable when this bit is set, the receive process stopped interrupt is enabled. when this bit is reset, the receive process stopped interrupt is disabled. 7 0x0 rw rxefie receive error frame interrupt enable when this bit is set, the receive error frame interrupt is enabled. when this bit is reset, the receive error frame interrupt is disabled. 6-0 - ro reserved downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 70 m9999-102207-1.9 bank 18 interrupt status register (0x02): isr this register contains the status bits for all qmu and other interrupt sources. when the corresponding enable bit is set, it causes the interrupt pin to be asserted. this register is usually read by the host cpu and device drivers during interrupt ser vice routine or polling. the register bits are not cleared when read. the user has to write 1 to clear bit default value r/w description 15 0x0 ro (w1c) lcis link change interrupt status when this bit is set, it indicates that the link status has changed from link up to link down, or link down to link up. this edge-triggered interrupt status is cleared by writing 1 to this bit. 14 0x0 ro (w1c) txis transmit status when this bit is set, it indicates that the txq mac has transmitted at least a frame on the mac interface and the qmu txq is ready for new frames from the host. this edge-triggered interrupt status is cleared by writing 1 to this bit. 13 0x0 ro (w1c) rxis receive interrupt status when this bit is set, it indicates that the qmu rxq has received a frame from the mac interface and the frame is ready for the host cpu to process. this edge-triggered interrupt status is cleared by writing 1 to this bit. 12 0x0 ro reserved 11 0x0 ro (w1c) rxois receive overrun interrupt status when this bit is set, it indicates that the receive overrun status has occurred. this edge-triggered interrupt status is cleared by writing 1 to this bit. 10 0x0 ro reserved 9 0x1 ro (w1c) txpsie transmit process stopped status when this bit is set, it indicates that the transmit process has stopped. this edge-triggered interrupt status is cleared by writing 1 to this bit. 8 0x1 ro (w1c) rxpsie receive process stopped status when this bit is set, it indicates that the receive process has stopped. this edge-triggered interrupt status is cleared by writing 1 to this bit. 7 0x0 ro (w1c) rxefie receive error frame interrupt status when this bit is set, it indicates that the receive error frame status has occurred. this edge-triggered interrupt status is cleared by writing 1 to this bit. 6-0 - ro reserved downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 71 m9999-102207-1.9 bank 18 receive status register (0x04): rxsr this register indicates the status of the current received frame and mirrors the receive status word of the re ceive frame in the rxq. bit default value r/w description 15 - ro rxfv receive frame valid when set, it indicates that the present frame in the receive packet memory is valid. the status information currently in this location is also valid. when clear, it indicates that there is either no pending receive frame or that the current frame is still in the process of receiving. 14-10 - ro reserved 9-8 - ro rxspn receive source port number when bit is set, this field indicates the source port where the packet was received. (setting bit 9 = 0 and bit 8 = 1 indicates the packet was received from port 1. setting bit 9 = 1 and bit 8 = 0 indicates that the packet was received from port 2. valid port is either port 1 or port 2. 7 - ro rxbf receive broadcast frame when set, it indicates that this frame has a broadcast address. 6 - ro rxmf receive multicast frame when set, it indicates that this frame has a multicast address (including the broadcast address). 5 - ro rxuf receive unicast frame when set, it indicates that this frame has a unicast address. 4 - ro reserved 3 - ro rxft receive frame type when set, it indicates that the frame is an ethernet-type frame (frame length is greater than 1500 bytes). when clear, it indicate that the frame is an ieee 802.3 frame. this bit is not valid for runt frames. 2 - ro rxtl receive frame too long when set, it indicates that the frame length exceeds the maximum size of 1916 bytes. frames that are too long are passed to the host only if the pass bad frame bit is set (bit 9 in rxcr register) note: frame too long is only a frame length indication and does not cause any frame truncation. 1 - ro rxrf receive runt frame when set, it indicates that a frame was damaged by a collision or premature termination before the collision window has passed. runt frames are passed to the host only if the pass bad frame bit is set (bit 9 in rxcr register). 0 - ro rxce receive crc error when set, it indicates that a crc error has occurred on the current received frame. a crc error frame is passed to the host only if the pass bad frame bit is set (bit 9 in rxcr register). downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 72 m9999-102207-1.9 bank 18 receive byte counter register (0x06): rxbc this register indicates the status of the current received frame and mirrors the receive byte c ount word of the receive frame in the rxq. bit default value r/w description 15-11 - ro reserved 10-0 - ro rxbc receive byte count receive byte count. bank 19 multicast table register 0 (0x00): mtr0 the 64-bit multicast table is used for group address filtering. this value is defined as the six most significant bits from crc circuit calculation result that is based on 48-bit of da input. the two most significant bits select one of the four registers to be used, while the others determine which bit within the register. multicast table register 0. bit default value r/w description 15-0 0x0000 rw mtr0 multicast table 0 when the appropriate bit is set, if the packet received with da matches the crc, the hashing function is received without being filtered. when the appropriate bit is cleared, the packet will drop. note: when the receive all (rxra) or receive multicast (rxrm) bit is set in the rxcr, all multicast addresses are received regardless of the multicast table value. bank 19 multicast table register 1 (0x02): mtr1 multicast table register 1. bit default value r/w description 15-0 0x0000 rw mtr0 multicast table 1 when the appropriate bit is set, if the packet received with da matches the crc, the hashing function is received without being filtered. when the appropriate bit is cleared, the packet will drop. note: when the receive all (rxra) or receive multicast (rxrm) bit is set in the rxcr, all multicast addresses are received regardless of the multicast table value. bank 19 multicast table register 2 (0x04): mtr2 multicast table register 2. bit default value r/w description 15-0 0x0000 rw mtr0 multicast table 2 when the appropriate bit is set, if the packet received with da matches the crc, the hashing function is received without being filtered. when the appropriate bit is cleared, the packet will drop. note: when the receive all (rxra) or receive multicast (rxrm) bit is set in the rxcr, all multicast addresses are received regardless of the multicast table value. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 73 m9999-102207-1.9 bank 19 multicast table register 3 (0x06): mtr3 multicast table register 3. bit default value r/w description 15-0 0x0000 rw mtr0 multicast table 3 when the appropriate bit is set, if the packet received with da matches the crc, the hashing function is received without being filtered. when the appropriate bit is cleared, the packet will drop. note: when the receive all (rxra) or receive multicast (rxrm) bit is set in the rxcr, all multicast addresses are received regardless of the multicast table value. banks 20 C 31: reserved except bank select register (0xe). bank 32 switch id and enable register (0x00): sider this register contains the switch id and the switch enable control. bit default r/w description 15-8 0x88 ro family id chip family id 7-4 0x0 ro chip id 0x0 is assigned to ksz8842m 3-1 0x1 ro revision id 0 0 rw start switch 1 = start the chip. 0 = switch is disabled. bank 32 switch global control register 1 (0x02): sgcr1 this register contains the global control for the switch function. bit default r/w description 15 0 rw pass all frames 1 = switch all packets including bad ones. used solely for debugging purposes. works in conjunction with sniffer mode only. 14 0 rw reserved 13 1 rw ieee 802.3x transmit direction flow control enable 1 = enables transmit direction flow control feature. 0 = will not enable transmit direction flow control feature. the switch will not generate any flow control packets. 12 1 rw ieee 802.3x receive direction flow control enable 1 = enables receive direction flow control feature. 0 = will not enable receive direction flow control feature. the switch will not react to any received flow control packets. 11 0 rw frame length field check 1 = checks frame length field in the ieee packets. if the actual length does not match, the packet will be dropped (for length/type field < 1500). downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 74 m9999-102207-1.9 bit default r/w description 10 1 rw aging enable 1 = enable age function in the chip. 0 = disable age function in the chip. 9 0 rw fast age enable 1 = turn on fast age (800us). 8 0 rw aggressive back-off enable 1 = enable more aggressive back off algorithm in half-duplex mode to enhance performance. this is not an ieee standard. 7-4 - rw reserved 3 0x0 rw pass flow control packet 1 = switch will not filter 802.1x flow control packets. 2-1 - rw reserved 0 0 rw link change age 1 = link change from link to no link will cause fast aging (<800us) to age address table faster. after an age cycle is complete, the age logic will return to normal (300 + 75 seconds). note: if any port is unplugged, all addresses will be automatically aged out. bank 32 switch global control register 2 (0x04): sgcr2 this register contains the global control for the switch function. bit default r/w description 15 0 rw 802.1q vlan enable 1 = 802.1q vlan mode is turned on. vlan table must be set up before the operation. 0 = 802.1q vlan is disabled. 14 0 rw igmp snoop enable on switch host port 1 = igmp snoop is enabled. all the igmp packets are forwarded to the switch host port. 0 = igmp snoop is disabled. 13 0 rw ipv6 mld snooping enable 1 = enable ipv6 mld snooping 12 0 rw ipv6 mld snooping option 1 = enable ipv6 mld snooping option 11 0 rw priority scheme select 0 = always tx higher priority packets first. 1 = weighted fair queueing enabled. when all four queues have packets waiting to transmit, the bandwidth allocation is q3:q2:q1:a0 = 8:4:2:1. if any queues are empty, the highest non-empty queue gets one more weighting. for example, if q2 is empty, q3:q1:q0 becomes (8+1): 0:2:1. 10-9 0x0 rw reserved 8 0 rw sniff mode select 1 =performs rx and tx sniff (both the source port and destination port need to match). 0 = performs rx or tx sniff (either the source port or destination port needs to match). this is the mode used to implement rx only sniff. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 75 m9999-102207-1.9 bit default r/w description 7 1 rw unicast port-vlan mismatch discard 1 = no packets can cross the vlan boundary. 0 = unicast packets (excluding unknown/multicast/broadcast) can cross the vlan boundary. 6 1 rw multicast storm protection disable 1 = broadcast storm protection does not include multicast packets. only da = ffffffffffff packets are regulated. 0 = broadcast storm protection includes da = ffffffffffff and da[40] = 1 packets. 5 1 rw back pressure mode 1 = carrier sense-based back pressure is selected. 0 = collision-based back pressure is selected. 4 1 rw flow control and back pressure fair mode 1 = fair mode is selected. in this mode, if a flow control port and a non-flow control port talk to the same destination port, packets from the non-flow control port may be dropped. this prevents the flow control port from being flow controlled for an extended period of time. 0 = in this mode, if a flow control port and a non-flow control port talk to the same destination port, the flow control port is flow controlled. this may not be fair to the flow control port. 3 0 rw no excessive collision drop 1 = the switch does not drop packets when 16 or more collisions occur. 0 = the switch drops packets when 16 or more collisions occur. 2 0 rw huge packet support 1 = accepts packet sizes up to 1916 bytes (inclusive). this bit setting overrides setting from bit 1 of the same register. 0 = the max packet size is determined by bit 1 of this register. 1 0 rw legal maximum packet size check enable 0 = accepts packet sizes up to 1536 bytes (inclusive). 1 = 1522 bytes for tagged packets, 1518 bytes for untagged packets. any packets larger than the specified value are dropped. 0 1 rw priority buffer reserve 1 = each port is pre-allocated 48 buffers, used exclusively for high priority (q3, q2, and q1) packets. effective only when the multiple queue feature is turned on. 0 = each port is pre-allocated 48 buffers used for all priority packets (q3, q2,q1, and q0). downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 76 m9999-102207-1.9 bank 32 switch global control register 3 (0x06): sgcr3 this register contains the global control for the switch function. bit default r/w description 15-8 0x63 rw broadcast storm protection rate bit [7:0] these bits, along with sgcr3[2:0], determine how many 64-byte blocks of packet data are allowed on an input port in a preset period. the period is 67ms for 100bt or 670ms for 10bt. the default is 1%. 7 0 rw repeater mode (note 1) 1 = enable repeater mode. 0 = normal mode. the switch supports only half duplex , 100bt in repeater mode. 6 0 rw switch host half-duplex mode the ksz8842m supports only half-duplex 100-baset throughput in repeater mode. 1 = enable host port interface half-duplex mode, this bit must be set for repeater mode 0 = enable host port interface full-duplex mode.. 5 0 rw switch flow control enable 1 = enable full-duplex flow control on switch host port. 0 = disable full-duplex flow control on switch host port 4 0 rw reserved 3 0 rw null vid replacement 1 = replaces null vid with port vid(12 bits). 0 = no replacement for null vid. 2-0 0x0 rw broadcast storm protection rate bit [10:8] these bits, along with sgcr3[15:8] determine how many 64-byte blocks of packet data are allowed on an input port in a preset period. the period is 67ms for 100bt or 670ms for 10bt. the default is 1%. rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63. note 1: user has to set bit 13 (100mbps), bit 12 (auto-negotiation disabled) and bit 8 (half duplex) in both p1mbcr and p2mbcr registers for repeater mode. bank 32 switch global control register 4 (0x08): sgcr4 this register contains the global control for the switch function. bit default r/w description 15-0 0x2400 rw reserved downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 77 m9999-102207-1.9 bank 32 switch global control register 5 (0x0a): sgcr5 this register contains the global control for the switch function. bit default r/w description 15 0 rw ledsel1 see the description in bit 9. 14-12 0x0 rw reserved 11-10 0x2 rw reserved 9 0 rw ledsel0 these two bits, ledsel1 and ledsel0, are used to select led mode. port n led indicators, (where n = 1 for port 1 and n =2 for port 2) defined as below: [ledsel1, ledsel0] [0, 0] [0, 1] pnled3 ------ ------ pnled2 link/act 100link/act pnled1 full_dpx/col 10link/act pnled0 speed full_dpx [ledsel1, ledsel0] [1, 0] [1, 1] pnled3 act ------ pnled2 link ------ pnled1 full_dpx/col ------ pnled0 speed ------ for repeater mode: [ledsel1, ledsel0] [0, 0] [0, 1] [1, 0] [1, 1] p1led3; p2led3 rpt_col; rpt_act ------ p1led2; p2led2 rpt_link3/rx; rpt_err3 ------ p1led1; p2led1 rpt_link2/rx; rpt_err2 ------ p1led0; p2led0 rpt_link1/rx; rpt_err1 ------ 8 0 rw reserved 7-0 0x35 rw reserved downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 78 m9999-102207-1.9 bank 33 switch global control register 6 (0x00): sgcr6 bit default r/w description 15-14 0x3 r/w tag_0x7 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee tag has a value of 0x7. 13-12 0x3 r/w tag_0x6 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee tag has a value of 0x6. 11-10 0x2 r/w tag_0x5 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee tag has a value of 0x5. 9-8 0x2 r/w tag_0x4 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee tag has a value of 0x4. 7-6 0x1 r/w tag_0x3 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee tag has a value of 0x3. 5-4 0x1 r/w tag_0x2 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee tag has a value of 0x2. 3-2 0x0 r/w tag_0x1 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee tag has a value of 0x1. 1-0 0x0 r/w tag_0x0 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee tag has a value of 0x0. bank 33 switch global control register 7 (0x02): sgcr7 bit default r/w description 15-8 0x00 r/w reserved 7 0 r/w unknown default port enable send packets with unknown destination address to specified ports in bits [2:0]. 1 = enable to send unknown da packet 6-3 - r/w reserved 2-0 0x7 r/w unknown packet default port(s) specify which ports to send packets with unknown destination addresses. feature is enabled by bit [7]. bit 2 for the host port, bit 1 for port 2, and bit 0 for port 1 banks 34 C 38: reserved except bank select register (0xe) bank 39 mac address register 1 (0x00): macar1 this register contains the mac address for the switch function. this mac address is used for sending pause frame. bit default r/w description 15-0 0x0010 rw maca[47:32] specifies mac address 1. this value has to be same as marh in bank2. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 79 m9999-102207-1.9 bank 39 mac address register 2 (0x02): macar2 this register contains the mac address for the switch function. this mac address is used for sending pause frame. bit default r/w description 15-0 0xa1ff rw maca[31:16] specifies mac address 2. this value has to be same as marm in bank2. bank 39 mac address register 3 (0x04): macar3 this register contains the mac address for the switch function. this mac address is used for sending pause frame. bit default r/w description 15-0 0xffff rw maca[15:0] specifies mac address 3. this value has to be same as marl in bank2. bank 40 tos priority control register 1 (0x00): tosr1 the ipv4/ipv6 tos priority control registers implement a fully decoded,128-bit dscp (differentiated services code point) register used to determine priority from the 6-bit tos (type of service) field in the ip header. the most significant 6 bits of the tos field are fully decoded into 64 possibilities, and the singular code that results is compared against the corresponding bits in the dscp register to determine the priority. this register contains the tos priority control for the switch function. bit default r/w description 15-14 0 rw dscp[15:14] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x1c. 13-12 0 r/w dscp[13:12] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x18. 11-10 0 r/w dscp[11:10] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x14. 9-8 0 r/w dscp[9:8] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x10. 7-6 0 r/w dscp[7:6] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x0c. 5-4 0 r/w dscp[5:4] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x08. 3-2 0 r/w dscp[3:2] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x04. 1-0 0 r/w dscp[1:0] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x00. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 80 m9999-102207-1.9 bank 40 tos priority control register 2 (0x02): tosr2 this register contains the tos priority control for the switch function. bit default r/w description 15-14 0 rw dscp[31:30] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x3c. 13-12 0 r/w dscp[29:28] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x38. 11-10 0 r/w dscp[27:26] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x34. 9-8 0 r/w dscp[25:24] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x30. 7-6 0 r/w dscp[23:22] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x2c. 5-4 0 r/w dscp[21:20] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x28. 3-2 0 r/w dscp[19:18] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x24. 1-0 0 r/w dscp[17:16] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x20. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 81 m9999-102207-1.9 bank 40 tos priority control register 3 (0x04): tosr3 this register contains the tos priority control for the switch function. bit default r/w description 15-14 0 rw dscp[47:46] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x5c. 13-12 0 r/w dscp[45:44] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x58. 11-10 0 r/w dscp[43:42] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x54. 9-8 0 r/w dscp[41:40] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x50. 7-6 0 r/w dscp[39:38] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x4c. 5-4 0 r/w dscp[37:36] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x48. 3-2 0 r/w dscp[35:34] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x44. 1-0 0 r/w dscp[33:32] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x40. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 82 m9999-102207-1.9 bank 40 tos priority control register 4 (0x06): tosr4 this register contains the tos priority control for the switch function. bit default r/w description 15-14 0 rw dscp[63:62] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x7c. 13-12 0 r/w dscp[61:60] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x78. 11-10 0 r/w dscp[59:58] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x74. 9-8 0 r/w dscp[57:56] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x70. 7-6 0 r/w dscp[55:54] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x6c. 5-4 0 r/w dscp[53:52] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x68. 3-2 0 r/w dscp[51:50] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x64. 1-0 0 r/w dscp[49:48] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x60. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 83 m9999-102207-1.9 bank 40 tos priority control register 5 (0x08): tosr5 this register contains the tos priority control for the switch function. bit default r/w description 15-14 0 rw dscp[79:78] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x9c. 13-12 0 r/w dscp[77:76] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x98. 11-10 0 r/w dscp[75:74] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x94. 9-8 0 r/w dscp[73:72] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x90. 7-6 0 r/w dscp[71:70] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x8c. 5-4 0 r/w dscp[69:68] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x88. 3-2 0 r/w dscp[67:66] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x84. 1-0 0 r/w dscp[65:64] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0x80. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 84 m9999-102207-1.9 bank 40 tos priority control register 6 (0x0a): tosr6 this register contains the tos priority control for the switch function. bit default r/w description 15-14 0 rw dscp[95:94] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xbc. 13-12 0 r/w dscp[93:92] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xb8. 11-10 0 r/w dscp[91:90] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xb4. 9-8 0 r/w dscp[89:88] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xb0. 7-6 0 r/w dscp[87:86] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xac. 5-4 0 r/w dscp[85:84] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xa8. 3-2 0 r/w dscp[83:82] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xa4. 1-0 0 r/w dscp[81:80] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xa0. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 85 m9999-102207-1.9 bank 41 tos priority control register 7 (0x00): tosr7 this register contains the tos priority control for the switch function. bit default r/w description 15-14 0 rw dscp[111:110] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xdc. 13-12 0 r/w dscp[109:108] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xd8. 11-10 0 r/w dscp[107:106] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xd4. 9-8 0 r/w dscp[105:104] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xd0. 7-6 0 r/w dscp[103:102] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xcc. 5-4 0 r/w dscp[101:100] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xc8. 3-2 0 r/w dscp[99:98] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xc4. 1-0 0 r/w dscp[97:96] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xc0. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 86 m9999-102207-1.9 bank 41 tos priority control register 8 (0x02): tosr8 this register contains the tos priority control for the switch function. bit default r/w description 15-14 0 rw dscp[127:126] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xfc 13-12 0 r/w dscp[125:124] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xf8. 11-10 0 r/w dscp[123:122] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xf4. 9-8 0 r/w dscp[121:120] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xf0. 7-6 0 r/w dscp[119:118] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xec. 5-4 0 r/w dscp[117:116] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xe8. 3-2 0 r/w dscp[115:114] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xe4. 1-0 0 r/w dscp[113:112] the value in this field is used as the frames priority when bits [7:2] of it ip tos/diffserv/traffic class value is 0xe0. bank 42 indirect access control register (0x00): iacr this register contains the indirect control for the switch function. bit default r/w description 15-13 0x0 rw reserved 12 0 rw read high. write low 1 = read cycle. 0 = write cycle. 11-10 0x0 rw table select 00 = static mac address table selected. 01 = vlan table selected. 10 = dynamic address table selected. 11 = mib counter selected. 9-0 0x000 rw indirect address bit 9-0 of indirect address. note: write iacr triggers a command. read or write access is determined by register bit 12. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 87 m9999-102207-1.9 bank 42 indirect access data register 1 (0x02): iadr1 this register contains the indirect data for the switch function. bit default r/w description 15-8 0x00 ro reserved 7 0 ro cpu read status only for dynamic and statistics counter reads. 1 = read is still in progress. 0 = read has completed. 6-3 0x0 ro reserved 2-0 0x0 ro indirect data bit 66-64 of indirect data. bank 42 indirect access data register 2 (0x04): iadr2 this register contains the indirect data for the switch function. bit default r/w description 15-0 0x0000 rw indirect data bit 47-32 of indirect data. bank 42 indirect access data register 3 (0x06): iadr3 this register contains the indirect data for the switch function. bit default r/w description 15-0 0x0000 rw indirect data bit 63-48 of indirect data. bank 42 indirect access data register 4 (0x08): iadr4 this register contains the indirect data for the switch function. bit default r/w description 15-0 0x0000 rw indirect data bit 15-0 of indirect data. bank 42 indirect access data register 5 (0x0a): iadr5 this register contains the indirect data for the switch function. bit default r/w description 15-0 0x0000 rw indirect data bit 31-16 of indirect data. bank 43: reserved except bank select register (0xe) downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 88 m9999-102207-1.9 bank 44 digital testing status register (0x00): dtsr this register contains the user defined register for the switch function. bit default r/w description 15-3 0x0000 ro reserved 2-0 0x0 ro reserved bank 44 analog testing status register (0x02): atsr this register contains the user defined register for the switch function. bit default r/w description 15-8 0x00 ro reserved 7-0 0x00 ro reserved bank 44 digital testing control register (0x04): dtcr this register contains the user defined register for the switch function. bit default r/w description 15-8 0x00 ro reserved 7-0 0x3f rw reserved bank 44 analog testing control register 0 (0x06): atcr0 this register contains the user defined register for the switch function. bit default r/w description 15-8 0x00 ro reserved 7-0 0x00 rw reserved bank 44 analog testing control register 1 (0x08): atcr1 this register contains the user defined register for the switch function. bit default r/w description 15-0 0x0000 rw reserved bank 44 analog testing control register 2 (0x0a): atcr2 this register contains the user defined register for the switch function. bit default r/w description 15-0 0x0000 rw reserved downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 89 m9999-102207-1.9 bank 45 phy 1 mii-register basi c control register (0x00): p1mbcr this register contains media independent interface (mii) register for switch port 1 as defined in the ieee 802.3 specification. bit default r/w description bit is same as: 15 0 ro soft reset not supported. 14 0 rw far-end loopback 1 = perform loopback as follows: start: rxp2/rxm2 (port 2) loop back: pmd/pma of port 1s phy end: txp2/txm2 (port 2) 0 = normal operation. bank 49 0x02 bit 8 13 0 rw force 100 1 = force 100mbps if an is disabled (bit 12) 0 = force 10mbps if an is disabled (bit 12) bank 49 0x02 bit 6 12 1 rw an enable 1 = auto-negotiation enabled. 0 = auto-negotiation disabled. bank 49 0x02 bit 7 11 0 rw power-down 1 = power-down. 0 = normal operation. bank 49 0x02 bit 11 10 0 ro isolate not supported. 9 0 rw restart an 1 = restart auto-negotiation. 0 = normal operation. bank 49 0x02 bit 13 8 0 rw force full duplex 1 = force full duplex. 0 = force half duplex. if an is disabled (bit 12) or an is enabled but failed. bank 49 0x02 bit 5 7 0 ro collision test not supported. 6 0 ro reserved. 5 1 r/w hp_mdix 1 = hp auto mdi-x mode. 0 = micrel auto mdi-x mode. bank 49 0x04 bit 15 4 0 rw force mdi-x 1 = force mdi-x. 0 = normal operation. bank 49 0x02 bit 9 3 0 rw disable mdi-x 1 = disable auto mdi-x. 0 = normal operation. bank 49 0x02 bit 10 2 0 rw reserved bank 49 0x02 bit 12 1 0 rw disable transmit 1 = disable transmit. 0 = normal operation. bank 49 0x02 bit 14 0 0 rw disable led 1 = disable led. 0 = normal operation. bank 49 0x02 bit 15 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 90 m9999-102207-1.9 bank 45 phy 1 mii-register basic status register (0x02): p1mbsr this register contains the mii register status for the switch port 1 function. bit default r/w description bit is same as: 15 0 ro t4 capable 1 = 100 base-t4 capable. 0 = not 100 base-t4 capable. 14 1 ro 100 full capable 1 = 100base-tx full-duplex capable. 0 = not 100base-tx full duplex capable. 13 1 ro 100 half capable 1 = 100base-tx half-duplex capable. 0 = not 100base-tx half-duplex capable. 12 1 ro 10 full capable 1 = 10base-t full-duplex capable. 0 = not 10base-t full-duplex capable. 11 1 ro 10 half capable 1 = 10base-t half-duplex capable. 0 = not 10base-t half-duplex capable. 10-7 0x0 ro reserved 6 0 ro preamble suppressed not supported. 5 0 ro an complete 1 = auto-negotiation complete. 0 = auto-negotiation not completed. bank 49 0x04 bit 6 4 0 ro reserved bank 49 0x04 bit 8 3 1 ro an capable 1 = auto-negotiation capable. 0 = not auto-negotiation capable. 2 0 ro link status 1 = link is up. 0 = link is down. bank49 0x04 bit 5 1 0 ro jabber test not supported. 0 0 ro extended capable 1 = extended register capable. 0 = not extended register capable. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 91 m9999-102207-1.9 bank 45 phy 1 phyid low register (0x04): phy1ilr this register contains the phy id (low) for the switch port 1 function. bit default r/w description 15-0 0x1430 ro phyid low low order phyid bits. bank 45 phy 1 phyid high register (0x06): phy1ihr this register contains the phy id (high) for the switch port 1 function. bit default r/w description 15-0 0x0022 ro phyid high high order phyid bits. bank 45 phy 1 auto-negotiation advertisement register (0x08): p1anar this register contains the auto-negotiation advertisement for the switch port 1 function. bit default r/w description bit is same as: 15 0 ro next page not supported. 14 0 ro reserved 13 0 ro remote fault not supported. 12-11 0x0 ro reserved 10 1 rw pause (flow control capability) 1 = advertise pause ability. 0 = do not advertise pause capability. bank 49 0x02 bit 4 9 0 rw reserved 8 1 rw adv 100 full 1 = advertise 100 full-duplex capable. 0 = do not advertise 100 full-duplex capability. bank49 0x02 bit 3 7 1 rw adv 100 half 1= advertise 100 half-duplex capable. 0 = do not advertise 100 half-duplex capability. bank49 0x02 bit 2 6 1 rw adv 10 full 1 = advertise 10 full-duplex capable. 0 = do not advertise 10 full-duplex capability. bank49 0x02 bit 1 5 1 rw adv 10 half 1 = advertise 10 half-duplex capable. 0 = do not advertise 10 half-duplex capability. bank49 0x02 bit 0 4-0 0x01 ro selector field 802.3 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 92 m9999-102207-1.9 bank 45 phy 1 auto-negotiation link partner ability register (0x0a): p1anlpr this register contains the auto-negotiation link partner ability for the switch port 1 function. bit default r/w description bit is same as: 15 0 ro next page not supported. 14 0 ro lp ack not supported. 13 0 ro remote fault not supported. 12-11 0x0 ro reserved 10 0 ro pause link partner pause capability. bank 49 0x04 bit 4 9 0 ro reserved 8 0 ro adv 100 full link partner 100 full capability. bank 49 0x04 bit 3 7 0 ro adv 100 half link partner 100 half capability. bank 49 0x04 bit 2 6 0 ro adv 10 full link partner 10 full capability. bank 49 0x04 bit 1 5 0 ro adv 10 half link partner 10 half capability. bank 49 0x04 bit 0 4-0 0x01 ro reserved bank 46 phy 2 mii-register basi c control register (0x00): p2mbcr this register contains media independent interface (mii) control for the switch function as defined in the ieee 802.3 specification. bit default r/w description bit is same as: 15 0 ro soft reset not supported. 14 0 rw far-end loopback 1 = perform loop back, as indicated (see figure15): start: rxp1/rxm1 (port 1) loop back: pmd/pma of port 2s phy end: txp1/txm1 (port 1) 0 = normal operation. bank 51 0x02 bit 8 13 0 rw force 100 1 = 100 mbps. 0 = 10 mbps. bank 51 0x02 bit 6 12 1 rw an enable 1 = auto-negotiation enabled. 0 = auto-negotiation disabled. bank 51 0x02 bit 7 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 93 m9999-102207-1.9 bit default r/w description bit is same as: 11 0 rw power down 1 = power down. 0 = normal operation. bank 51 0x02 bit 11 10 0 ro isolate not supported. 9 0 rw restart an 1 = restart auto-negotiation. 0 = normal operation, bank 51 0x02 bit 13 8 0 rw force full duplex 1 = full duplex. 0 = half duplex. bank 51 0x02 bit 5 7 0 ro collision test not supported. 6 0 ro reserved 5 1 r/w hp_mdix 1 = hp auto mdi-x mode. 0 = micrel auto mdi-x mode. bank 51 0x04 bit 15 4 0 rw force mdi-x 1 = force mdi-x. 0 = normal operation. bank 51 0x02 bit 9 3 0 rw disable mdi-x 1 = disable auto mdi-x. 0 = normal operation. bank 51 0x02 bit 10 2 0 rw reserved bank 51 0x02 bit 12 1 0 rw disable transmit 1 = disable transmit. 0 = normal operation. bank 51 0x02 bit 14 0 0 rw disable led 1 = disable led. 0 = normal operation. bank 51 0x02 bit 15 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 94 m9999-102207-1.9 bank 46 phy 2 mii-register basic status register (0x02): p2mbsr this register contains the mii register for the switch port 2 function. bit default r/w description bit is same as: 15 0 ro t4 capable 0 = not 100 base-t4 capable. 14 1 ro 100 full capable 1 = 100base-tx full-duplex capable. 0 = not 100base-tx full-duplex capable. 13 1 ro 100 half capable 1 = 100base-tx half-duplex capable. 0 = not 100base-tx half-duplex capable. 12 1 ro 10 full capable 1 = 10base-t full-duplex capable. 0 = not 10base-t full-duplex capable. 11 1 ro 10 half capable 1 = 10base-t half-duplex capable. 0 = not 10base-t half-duplex capable. 10-7 0x0 ro reserved 6 0 ro preamble suppressed not supported. 5 0 ro an complete 1 = auto-negotiation complete. 0 = auto-negotiation not complete. bank 51 0x04 bit 6 4 0 ro reserved bank 51 0x04 bit 8 3 1 ro an capable 1 = auto-negotiation capable. 0 = not auto-negotiation capable. 2 0 ro link status 1 = link is up. 0 = link is down. bank 51 0x04 bit 5 1 0 ro jabber test not supported. 0 0 ro extended capable 0 = not extended register capable. bank 46 phy 2 phyid low register (0x04): phy2ilr this register contains the phy id (low) for the switch port 2 function. bit default r/w description 15-0 0x1430 ro phyid low low order phyid bits. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 95 m9999-102207-1.9 bank 46 phy 2 phyid high register (0x06): phy2ihr this register contains the phy id (high) for the switch port 2 function. bit default r/w description 15-0 0x0022 ro phyid high high order phyid bits. bank 46 phy 2 auto-negotiation advertisement register (0x08): p2anar this register contains the auto-negotiation advertisement for the switch port 2 function. bit default r/w description bit is same as: 15 0 ro next page not supported. 14 0 ro reserved 13 0 ro remote fault not supported. 12-11 0x0 ro reserved 10 1 rw pause 1 = advertise pause capability. 0 = do not advertise pause capability. bank 51 0x02 bit 4 9 0 rw reserved 8 1 rw adv 100 full 1 = advertise 100 full-duplex capability. 0 = do not advertise 100 full-duplex capability. bank 51 0x02 bit 3 7 1 rw adv 100 half 1 = advertise 100 half-duplex capability. 0 = do not advertise 100 half-duplex capability. bank 51 0x02 bit 2 6 1 rw adv 10 full 1 = advertise 10 full-duplex capability. 0 = do not advertise 10 full-duplex capability. bank 51 0x02 bit 1 5 1 rw adv 10 half 1= advertise 10 half-duplex capability. 0 = do not advertise 10 half-duplex capability. bank 51 0x02 bit 0 4-0 0x01 ro selector field 802.3 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 96 m9999-102207-1.9 bank 46 phy 2 auto-negotiation link partner ability register (0x0a): p2anlpr this register contains the auto-negotiation link partner ability for the switch port 2 function. bit default r/w description bit is same as: 15 0 ro next page not supported. 14 0 ro lp ack not supported. 13 0 ro remote fault not supported. 12-11 0x0 ro reserved 10 0 ro pause link partner pause capability. bank 51 0x04 bit 4 9 0 ro reserved 8 0 ro adv 100 full link partner 100 full capability. bank 51 0x04 bit 3 7 0 ro adv 100 half link partner 100 half capability. bank 51 0x04 bit 2 6 0 ro adv 10 full link partner 10 full capability. bank 51 0x04 bit 1 5 0 ro adv 10 half link partner 10 half capability. bank 51 0x04 bit 0 4-0 0x01 ro reserved bank 47 phy1 linkmd control/status (0x00): p1vct this register contains the linkmd control and status information of phy 1. bit default r/w description bit is same as: 15 0 rw (self- clear) vct_enable 1 = cable diagnostic test is enabled. it is self- cleared after the vct test is done. 0 = indicates that the cable diagnostic test is completed and the status information is valid for read. bank 49 0x00 bit 12 14-13 0x0 ro vct_result [00] = normal condition. [01] = open condition detected in the cable. [10] = short condition detected in the cable. [11] = cable diagnostic test failed. bank 49 0x00 bit 14-13 12 - ro vct 10m short 1 = less than 10m short. bank 49 0x00 bit 15 11-9 0x0 ro reserved 8-0 0x000 ro vct_fault_count distance to the fault. the distance is approximately 0.4m*vct_fault_count. bank 49 0x00 bit 8-0 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 97 m9999-102207-1.9 bank 47 phy1 special control/status register (0x02): p1phyctrl this register contains the control and status information of phy1. bit default r/w description bit is same as: 15-6 0x000 ro reserved 5 0 ro polarity reverse (polrvs) 1 = polarity is reversed. 0 = polarity is not reversed. bank 49 0x04 bit 13 4 0 ro mdi-x status (mdix_st) 1 = mdi 0 = mdi-x bank 49 0x04 bit 7 3 0 rw force link (force_lnk) 1 = force link pass. 0 = normal operation. bank 49 0x00 bit 11 2 1 rw power saving (pwrsave) 1 = disable power saving. 0 = enable power saving. bank 49 0x00 bit 10 1 0 rw remote (near-end) loopback (rlb) 1 = perform remote loopback at port 1's phy (rxp1/rxm1 -> txp1/txm1, see figure 16) 0 = normal operation bank 49 0x00 bit 9 0 0 rw reserved bank 47 phy2 linkmd control/status (0x04): p2vct this register contains the linkmd control and status information of phy 2. bit default r/w description bit is same as: 15 0 (self-clear) rw vct_enable 1 = the cable diagnostic test is enabled. it is self-cleared after the vct test is done. 0 = it indicates the cable diagnostic test is completed and the status information is valid for read. bank 51 0x00 bit 12 14-13 0x0 ro vct_result [00] = normal condition. [01] = open condition detected in the cable. [10] = short condition detected in the cable. [11] = cable diagnostic test failed. bank 51 0x00 bit 14-13 12 - ro vct 10m short 1 = less than 10m short. bank 51 0x00 bit 15 11-9 0x0 ro reserved 8-0 0x000 ro vct_fault_count distance to the fault. the distance is approximately 0.4m*vct_fault_count. bank 51 0x00 bit 8-0 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 98 m9999-102207-1.9 bank 47 phy2 special control/status register (0x06): p2phyctrl this register contains the control and status information of phy2. bit default r/w description bit is same as: 15-6 0x000 ro reserved 5 0 ro polarity reverse (polrvs) 1 = polarity is reversed. 0 = polarity is not reversed. bank 51 0x04 bit 13 4 0 ro mdix status (mdix_st) 1 = mdi 0 = mdi-x bank 51 0x04 bit 7 3 0 rw force link (force_lnk) 1 = force link pass. 0 = normal operation. bank 51 0x00 bit 11 2 1 rw power saving (pwrsave) 1 = disable power saving. 0 = enable power saving. bank 51 0x00 bit 10 1 0 rw remote (near-end) loopback (rlb) 1 = perform remote loopback at port 2's phy(rxp2/rxm2 -> txp2/txm2. see figure 16) 0 = normal operation bank 51 0x00 bit 9 0 0 rw reserved downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 99 m9999-102207-1.9 bank 48 port 1 control register 1 (0x00): p1cr1 this register contains the global per port control for the switch function. bit default r/w description 15-8 0x00 ro reserved 7 0 rw broadcast storm protection enable 1 = enable broadcast storm protection for ingress packets on the port. 0 = disable broadcast storm protection. 6 0 rw diffserv priority classification enable 1= enable diffserv priority classification for ingress packets on the port. 0 = disable diffserv function. 5 0 rw 802.1p priority classification enable 1= enable 802.1p priority classification for ingress packets on the port. 0 = disable 802.1p. 4-3 0x0 rw port-based priority classification 00 - ingress packets on port are classified as priority 0 queue if diffserv or 802.1p classification is not enabled or fails to classify. 01 - ingress packets on port are classified as priority 1 queue if diffserv or 802.1p classification is not enabled or fails to classify. 10 - ingress packets on port are classified as priority 2 queue if diffserv or 802.1p classification is not enabled or fails to classify. 11 - ingress packets on port are classified as priority 3 queue if diffserv or 802.1p classification is not enabled or fails to classify. note: diffserv, 802.1p and port priority can be enabled at the same time. the ored result of 802.1p and dscp overwrites the port priority. 2 0 rw tag insertion 1 = when packets are output on the port, the switch adds 802.1p/q tags to packets without 802.1p/q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress ports port vid. 0 = disable tag insertion. 1 0 rw tag removal 1 = when packets are output on the port, the switch removes 802.1p/q tags from packets with 802.1p/q tags when received. the switch will not modify packets received without tags. 0 = disable tag removal. 0 0 rw tx multiple queues select enable 1 = the port output queue is split into four priority queues. 0 = single output queue on the port. there is no priority differentiation even though packets are classified into high or low priority. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 100 m9999-102207-1.9 bank 48 port 1 control register 2 (0x02): p1cr2 this register contains the global per port control for the switch function. bit default r/w description 15 0 rw reserved 14 0 rw ingress vlan filtering 1= the switch discards packets whose vid port membership in vlan table bits [18:16] does not include the ingress port vid. 0 = no ingress vlan filtering. 13 0 rw discard non pvid packets 1 = the switch discards packets whose vid does not match the ingress port default vid. 0 = no packets are discarded. 12 0 rw force flow control 1 = always enable flow control on the port, regardless of an result. 0 = the flow control is enabled based on an result. 11 0 rw back pressure enable 1 = enable ports half-duplex back pressure. 0 = disable ports half-duplex back pressure. 10 1 rw transmit enable 1 = enable packet transmission on the port. 0 = disable packet transmission on the port. 9 1 rw receive enable 1 = enable packet reception on the port. 0 = disable packet reception on the port. 8 0 rw learning disable 1 = disable switch address learning capability. 0 = enable switch address learning. 7 0 rw sniffer port 1 = port is designated as a sniffer port and transmits packets that are monitored. 0 = port is a normal port. 6 0 rw receive sniff 1 = all packets received on the port are marked as monitored packets and forwarded to the designated sniffer port. 0 = no receive monitoring. 5 0 rw transmit sniff 1 = all packets transmitted on the port are marked as monitored packets and forwarded to the designated sniffer port. 0 = no transmit monitoring. 4 0 rw reserved 3 0 rw user priority ceiling 1 = if the packets priority field is greater than the user priority field in the port vid control register bit[15:13], replace the packets priority field with the user priority field in the port vid control register bit[15:13]. 0 = do no compare and replace the packets priority field. 2-0 0x7 rw port vlan membership define the ports port vlan membership. bit 2 stands for the host port, bit 1 for port 2, and bit 0 for port 1. the port can only communicate within the membership. a 1 includes a port in the membership; a 0 excludes a port from the membership. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 101 m9999-102207-1.9 bank 48 port 1 vid control register (0x04): p1vidcr this register contains the global per port control for the switch function. bit default r/w description 15-13 0x0 rw default tag[15:13] ports default tag, containing user priority field bits. 12 0 rw default tag[12] ports default tag, containing cfi bit. 11-0 0x001 rw default tag[11:0] ports default tag, containing vid[11:0]. note: this vid control register serves two purposes: 1. associated with the ingress untagged packets, and used for egress tagging. 2. default vid for the ingress untagged or null-vid-tagged packets, and used for address lookup. bank 48 port 1 control register 3 (0x06): p1cr3 bit default r/w description 15-5 0x000 ro reserved 4 0x0 rw reserved 3-2 0x0 rw ingress limit mode these bits determine what kinds of frames are limited and counted against ingress limiting as follows: 00 = limit and count all frames. 01 = limit and count broadcast, multicast, and flooded unicast frames. 10 = limit and count broadcast and multicast frames only. 11 = limit and count broadcast frames only. 1 0 rw count ifg count ifg bytes. 1= each frames minimum inter frame gap. (ifg) bytes (12 per frame) are included in ingress and egress rate limiting calculations. 0= ifg bytes are not counted. 0 0 rw count preamble count preamble bytes. 1 = each frames preamble bytes (8 per frame) are included in ingress and egress rate limiting calculations. 0 = preamble bytes are not counted. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 102 m9999-102207-1.9 bank 48 port 1 ingress rate control register (0x08): p1ircr bit default r/w description 15-12 0x0 rw ingress pri3 rate priority 3 frames will be discarded after the ingress rate selected as shown below is reached or exceeded. 0000 = not limited (default) 0001 = 64kbps 0010 = 128kbps 0011 = 256kbps 0100 = 512kbps 0101 = 1mbps 0110 = 2mbps 0111 = 4mbps 1000 = 8mbps 1001 = 16mbps 1010 = 32mbps 1011 = 48mbps 1100 = 64 mbps 1101 = 72mbps 1110 = 80mbps 1111 = 88mbps note: for 10bt, rate settings above 10mbps are set to the default value 0000 (not limited). 11-8 0x0 rw ingress pri2 rate priority 2 frames will be discarded after the ingress rate selected as shown below is reached or exceeded. 0000 = not limited (default) 0001 = 64kbps 0010 = 128kbps 0011 = 256kbps 0100 = 512kbps 0101 = 1mbps 0110 = 2mbps 0111 = 4mbps 1000 = 8mbps 1001 = 16mbps 1010 = 32mbps 1011 = 48mbps 1100 = 64 mbps 1101 = 72mbps 1110 = 80mbps 1111 = 88mbps note: for 10bt, rate settings above 10mbps are set to the default value 0000 (not limited). downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 103 m9999-102207-1.9 bit default r/w description 7-4 0x0 rw ingress pri1 rate priority 1 frames will be discarded after the ingress rate selected as shown below is reached or exceeded. 0000 = not limited (default) 0001 = 64kbps 0010 = 128kbps 0011 = 256kbps 0100 = 512kbps 0101 = 1mbps 0110 = 2mbps 0111 = 4mbps 1000 = 8mbps 1001 = 16mbps 1010 = 32mbps 1011 = 48mbps 1100 = 64 mbps 1101 = 72mbps 1110 = 80mbps 1111 = 88mbps note: for 10bt, rate settings above 10mbps are set to the default value 0000 (not limited). 3-0 0x0 rw ingress pri0 rate priority 0 frames will be discarded after the ingress rate selected as shown below is reached or exceeded. 0000 = not limited (default) 0001 = 64kbps 0010 = 128kbps 0011 = 256kbps 0100 = 512kbps 0101 = 1mbps 0110 = 2mbps 0111 = 4mbps 1000 = 8mbps 1001 = 16mbps 1010 = 32mbps 1011 = 48mbps 1100 = 64 mbps 1101 = 72mbps 1110 = 80mbps 1111 = 88mbps note: for 10bt, rate settings above 10mbps are set to the default value 0000 (not limited). downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 104 m9999-102207-1.9 bank 48 port 1 egress rate control register (0x0a): p1ercr bit default r/w description 15-12 0x0 rw egress pri3 rate egress data rate limit for priority 3 frames. output traffic from this priority queue is shaped according to the egress rate selected below: 0000 = not limited (default) 0001 = 64kbps 0010 = 128kbps 0011 = 256kbps 0100 = 512kbps 0101 = 1mbps 0110 = 2mbps 0111 = 4mbps 1000 = 8mbps 1001 = 16mbps 1010 = 32mbps 1011 = 48mbps 1100 = 64 mbps 1101 = 72mbps 1110 = 80mbps 1111 = 88mbps notes: for 10bt, rate settings above 10mbps are set to the default value 0000 (not limited). when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 11-8 0x0 rw egress pri2 rate egress data rate limit for priority 2 frames. output traffic from this priority queue is shaped according to the egress rate selected below: 0000 = not limited (default) 0001 = 64kbps 0010 = 128kbps 0011 = 256kbps 0100 = 512kbps 0101 = 1mbps 0110 = 2mbps 0111 = 4mbps 1000 = 8mbps 1001 = 16mbps 1010 = 32mbps 1011 = 48mbps 1100 = 64 mbps 1101 = 72mbps 1110 = 80mbps 1111 = 88mbps notes: for 10bt, rate settings above 10mbps are set to the default value 0000 (not limited). when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 105 m9999-102207-1.9 bit default r/w description 7-4 0x0 rw egress pri1 rate egress data rate limit for priority 1 frames. output traffic from this priority queue is shaped according to the egress rate selected below: 0000 = not limited (default) 0001 = 64kbps 0010 = 128kbps 0011 = 256kbps 0100 = 512kbps 0101 = 1mbps 0110 = 2mbps 0111 = 4mbps 1000 = 8mbps 1001 = 16mbps 1010 = 32mbps 1011 = 48mbps 1100 = 64 mbps 1101 = 72mbps 1110 = 80mbps 1111 = 88mbps notes: for 10bt, rate settings above 10mbps are set to the default value 0000 (not limited). when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 3-0 0x0 rw egress pri0 rate egress data rate limit for priority 0 frames. output traffic from this priority queue is shaped according to the egress rate selected below: 0000 = not limited (default) 0001 = 64kbps 0010 = 128kbps 0011 = 256kbps 0100 = 512kbps 0101 = 1mbps 0110 = 2mbps 0111 = 4mbps 1000 = 8mbps 1001 = 16mbps 1010 = 32mbps 1011 = 48mbps 1100 = 64 mbps 1101 = 72mbps 1110 = 80mbps 1111 = 88mbps notes: for 10bt, rate settings above 10mbps are set to the default value 0000 (not limited). when multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 106 m9999-102207-1.9 bank 49 port 1 phy special control/status, linkmd (0x00): p1scslmd bit default r/w description bit is same as: 15 0 ro vct_10m_short 1 = less than 10 meter short. bank 47 0x00 bit 12 14-13 0x0 ro vct_result vct result. [00] = normal condition. [01] = open condition has been detected in cable. [10] = short condition has been detected in cable. [11] = cable diagnostic test is failed. bank 47 0x00 bit 14-13 12 0 rw sc vct_en vct enable. 1 = the cable diagnostic test is enabled. it is self- cleared after the vct test is done. 0 = it indicates the cable diagnostic test is completed and the status information is valid for read. bank 47 0x00 bit 15 11 0 rw force_lnk force link. 1 = force link pass. 0 = normal operation. bank 47 0x02 bit 3 10 1 rw pwrsave power-saving. 1 = disable power saving. 0 = enable power saving. bank 47 0x02 bit 2 9 0 rw remote (near-end) loopback (rlb) 1 = perform remote loopback at port 1's phy (rxp1/rxm1 -> txp1/txm1, see figure 16) 0 = normal operation bank 47 0x02 bit 1 8-0 0x000 ro vct_fault_count vct fault count. distance to the fault. its approximately 0.4m*vct_fault_count. bank 47 0x00 bit 8-0 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 107 m9999-102207-1.9 bank 49 port 1 control register 4 (0x02): p1cr4 this register contains the global per port control for the switch function. bit default r/w description bit is same as: 15 0 rw led off 1 = turn off all of the port 1 leds (p1led3, p1led2, p1led1, p1led0). these pins are driven high if this bit is set to one. 0 = normal operation. bank 45 0x00 bit 0 14 0 rw txids 1 = disable the ports transmitter. 0 = normal operation. bank 45 0x00 bit1 13 0 rw restart an 1 = restart auto-negotiation. 0 = normal operation. bank 45 0x00 bit 9 12 0 rw reserved bank 45 0x00 bit 2 11 0 rw power down 1 = power down. 0 = normal operation. bank 45 0x00 bit 11 10 0 rw disable auto mdi/mdi-x 1 = disable auto mdi/mdi-x function. 0 = enable auto mdi/mdi-x function. bank 45 0x00 bit 3 9 0 rw force mdi-x 1= if auto mdi/mdi-x is disabled, force phy into mdi-x mode. 0 = do not force phy into mdi-x mode. bank 45 0x00 bit 4 8 0 rw far-end loopback 1 = perform loopback, as indicated: start: rxp2/rxm2 (port 2). loopback: pmd/pma of port 1s phy. end: txp2/txm2 (port 2). 0 = normal operation. bank 45 0x00 bit 14 7 1 rw auto negotiation enable 1 = auto negotiation is enabled. 0 = disable auto negotiation, speed, and duplex are decided by bits 6 and 5 of the same register. bank 45 0x00 bit 12 6 0 rw force speed 1 = force 100bt if an is disabled (bit 7). 0 = force 10bt if an is disabled (bit 7). bank 45 0x00 bit 13 5 0 rw force duplex 1 = force full duplex if (1) an is disabled or (2) an is enabled but failed. 0 = force half duplex if (1) an is disabled or (2) an is enabled but failed. bank 45 0x00 bit 8 4 1 rw advertised flow control capability. 1 = advertise flow control (pause) capability. 0 = suppress flow control (pause) capability from transmission to link partner. bank 45 0x08 bit 10 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 108 m9999-102207-1.9 bit default r/w description bit is same as: 3 1 rw advertised 100bt full-duplex capability. 1 = advertise 100bt full-duplex capability. 0 = suppress 100bt full-duplex capability from transmission to link partner. bank 45 0x08 bit 8 2 1 rw advertised 100bt half-duplex capability. 1 = advertise 100bt half-duplex capability. 0 = suppress 100bt half-duplex capability from transmission to link partner. bank 45 0x08 bit 7 1 1 rw advertised 10bt full-duplex capability. 1 = advertise 10bt full-duplex capability. 0 = suppress 10bt full-duplex capability from transmission to link partner. bank 45 0x08 bit 6 0 1 rw advertised 10bt half-duplex capability. 1 = advertise 10bt half-duplex capability. 0 = suppress 10bt half-duplex capability from transmission to link partner. bank 45 0x08 bit 5 bank 49 port 1 status register (0x04): p1sr this register contains the global per port status for the switch function. bit default r/w description bit is same as: 15 1 rw hp_mdix 1 = hp auto mdi-x mode. 0 = micrel auto mdi-x mode. bank 45 0x00 bit 5 14 0 ro reserved 13 0 ro polarity reverse 1 = polarity is reversed. 0 = polarity is not reversed. bank 47 0x02 bit 5 12 0 ro receive flow control enable 1 = receive flow control feature is active. 0 = receive flow control feature is inactive. 11 0 ro transmit flow control enable 1 = transmit flow control feature is active. 0 = transmit flow control feature is inactive. 10 0 ro operation speed 1 = link speed is 100mbps. 0 = link speed is 10mbps. 9 0 ro operation duplex 1 = link duplex is full. 0 = link duplex is half. 8 0 ro reserved bank 45 0x02 bit 4 7 0 ro mdi-x status 1 = mdi. 0 = mdi-x. bank 47 0x02 bit 4 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 109 m9999-102207-1.9 bit default r/w description bit is same as: 6 0 ro an done 1 = an done. 0 = an not done. bank 45 0x02 bit 5 5 0 ro link good 1 = link good. 0 = link not good. bank 45 0x02 bit 2 4 0 ro partner flow control capability. 1 = link partner flow control (pause) capable. 0 = link partner not flow control (pause) capable. bank 45 0x0a bit 10 3 0 ro partner 100bt full-duplex capability. 1 = link partner 100bt full-duplex capable. 0 = link partner not 100bt full-duplex capable. bank 45 0x0a bit 8 2 0 ro partner 100bt half-duplex capability. 1 = link partner 100bt half-duplex capable. 0= link partner not 100bt half-duplex capable. bank 45 0x0a bit 7 1 0 ro partner 10bt full-duplex capability. 1= link partner 10bt full-duplex capable. 0 = link partner not 10bt full-duplex capable. bank 45 0x0a bit 6 0 0 ro partner 10bt half-duplex capability. 1 = link partner 10bt half-duplex capable. 0 = link partner not 10bt half-duplex capable. bank 45 0x0a bit 5 bank 50 port 2 control register 1 (0x00): p2cr1 this register contains the global per port control for the switch function. see description in p1cr1, b ank 48 (0x00) bank 50 port 2 control register 2 (0x02): p2cr2 this register contains the global per port control for the switch function. see description in p1cr2, b ank 48 (0x02) bank 50 port 2 vid control register (0x04): p2vidcr this register contains the global per port control for the sw itch function. see description in p1vidcr, bank 48 (0x04) bank 50 port 2 control register 3 (0x06): p2cr3 this register contains the global per port control for the switch function. see description in p1cr3, b ank 48 (0x06) bank 50 port 2 ingress rate control register (0x08): p2ircr this register contains per port ingress rate control. see description in p1ircr, bank 48 (0x08) bank 50 port 2 egress rate control register (0x0a): p2ercr this register contains per port egress rate control. see description in p1ercr, bank 48 (0x0a) downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 110 m9999-102207-1.9 bank 51 port 2 phy special control/status, linkmd (0x00): p2scslmd bit default r/w description bit is same as: 15 0 ro vct_10m_short 1 = less than 10 meter short. bank 47 0x04 bit 12 14-13 0x0 ro vct_result vct result. [00] = normal condition. [01] = open condition has been detected in the cable. [10] = short condition has been detected in the cable. [11] = cable diagnostic test has failed. bank 47 0x04 bit 14-13 12 0 rw sc vct_en vct enable. 1 = the cable diagnostic test is enabled. it is self- cleared after the vct test is done. 0 = it indicates the cable diagnostic test is completed and the status information is valid for read bank 47 0x04 bit 15 11 0 rw force_lnk force link. 1 = force link pass. 0 = normal operation. bank 47 0x06 bit 3 10 1 rw pwrsave power-saving. 1 = disable power saving. 0 = enable power saving. bank 47 0x06 bit 2 9 0 rw remote (near-end) loopback (rlb) 1 = perform remote loopback at port 2's phy (rxp2/rxm2 -> txp2/txm2, see figure 16) 0 = normal operation bank 47 0x06 bit 1 8-0 0x000 ro vct_fault_count vct fault count. the distance to the fault is approximately 0.4m*vct_fault_count. bank 47 0x04 bit 8-0 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 111 m9999-102207-1.9 bank 51 port 2 control register 4 (0x02): p2cr4 this register contains the global per port control for the switch function. bit default r/w description bit is same as: 15 0 rw led off 1 = turn off all of the port 2 leds (p2led3, p2led2, p2led1, p2led0). these pins are driven high if this bit is set to 1. 0 = normal operation. bank 46 0x00 bit 0 14 0 rw txids 1 = disable ports transmitter. 0 = normal operation. bank 46 0x00 bit 1 13 0 rw restart an 1 = restart auto-negotiation. 0 = normal operation. bank 46 0x00 bit 9 12 0 rw reserved bank 46 0x00 bit 2 11 0 rw power down 1 = power-down. 0 = normal operation. bank 46 0x00 bit 11 10 0 rw disable auto mdi/mdi-x 1= disable auto mdi/mdi-x function. 0= enable auto mdi/mdi-x function. bank 46 0x00 bit 3 9 0 rw force mdi-x 1 = if auto mdi/mdi-x is disabled, force phy into mdi-x mode. 0 = do not force phy into mdi-x mode. bank 46 0x00 bit 4 8 0 rw far-end loopback 1 = perform loopback, as indicated (see figure 15): start: rxp1/rxm1 (port 1). loopback: pmd/pma of port 2s phy. end: txp1/txm1 (port 1). 0 = normal operation. bank 46 0x00 bit 14 7 1 rw auto negotiation enable 0 = disable auto negotiation, speed and duplex are decided by bits 6 and 5 of the same register. 1 = auto negotiation is on. bank 46 0x00 bit 12 6 0 rw force speed 1 = force 100bt if an is disabled (bit 7). 0 = force 10bt if an is disabled (bit 7). bank 46 0x00 bit 13 5 0 rw force duplex 1 = force full duplex if (1) an is disabled or (2) an is enabled but failed. 0 = force half duplex if (1) an is disabled or (2) an is enabled but failed. bank 46 0x00 bit 8 4 1 rw advertised flow control capability. 1 = advertise flow control (pause) capability. 0 = suppress flow control (pause) capability from transmission to the link partner. bank 46 0x08 bit 10 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 112 m9999-102207-1.9 bit default r/w description bit is same as: 3 1 rw advertised 100bt full-duplex capability. 1 = advertise 100bt full-duplex capability. 0 = suppress 100bt full-duplex capability from transmission to the link partner. bank 46 0x08 bit 8 2 1 rw advertised 100bt half-duplex capability. 1 = advertise 100bt half-duplex capability. 1 = suppress 100bt half-duplex capability from transmission to the link partner. bank 46 0x08 bit 7 1 1 rw advertised 10bt full-duplex capability. 1 = advertise 10bt full-duplex capability. 0 = suppress 10bt full-duplex capability from transmission to the link partner. bank 46 0x08 bit 6 0 1 rw advertised 10bt half-duplex capability. 1 = advertise 10bt half-duplex capability. 0 = suppress 10bt half-duplex capability from transmission to the link partner. bank 46 0x08 bit 5 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 113 m9999-102207-1.9 bank 51 port 2 status register (0x04): p2sr this register contains the global per port status for the switch function. bit default r/w description bit is same as: 15 1 rw hp_mdix 1 = hp auto mdi-x mode. 0 = micrel auto mdi-x mode. bank 46 0x00 bit 5 14 0 ro reserved 13 0 ro polarity reverse 1 = polarity is reversed. 0 = polarity is not reversed. bank 47 0x06 bit 5 12 0 ro receive flow control enable 1 = receive flow control feature is active. 0 = receive flow control feature is inactive. 11 0 ro transmit flow control enable 1 = transmit flow control feature is active. 0 = transmit flow control feature is inactive. 10 0 ro operation speed 1 = link speed is 100mbps. 0 = link speed is 10mbps. 9 0 ro operation duplex 1 = link duplex is full. 0 = link duplex is half. 8 0 ro reserved bank 46 0x02 bit 4 7 0 ro mdi-x status 1 = mdi. 0 = mdi-x. bank 47 0x06 bit 4 6 0 ro an done 1 = an done. 0 = an not done. bank 46 0x02 bit 5 5 0 ro link good 1 = link good. 0 = link not good. bank 46 0x02 bit 2 4 0 ro partner flow control capability. 1 = link partner flow control (pause) capable. 0 = link partner not flow control (pause) capable. bank 46 0x0a bit 10 3 0 ro partner 100bt full-duplex capability. 1 = link partner 100bt full-duplex capable. 0 = link partner not 100bt full-duplex capable. bank 46 0x0a bit 8 2 0 ro partner 100bt half duplex capability. 1 = link partner 100bt half-duplex capable. 0 = link partner not 100bt half-duplex capable. bank 46 0x0a bit 7 1 0 ro partner 10bt full-duplex capability. 1 = link partner 10bt full-duplex capable. 0 = link partner not 10bt full-duplex capable. bank 46 0x0a bit 6 0 0 ro partner 10bt half-duplex capability. 1 = link partner 10bt half-duplex capable. 0 = link partner not 10bt half-duplex capable. bank 46 0x0a bit 5 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 114 m9999-102207-1.9 bank 52 host port control register 1 (0x00): p3cr1 this register contains the global per port control for the switch function. see description in p1cr1, b ank 48 (0x00). bank 52 host port control register 2 (0x02): p3cr2 this register contains the global per port control for the switch function. bit default r/w description 15 0 reserved 14 0 rw ingress vlan filtering 1 = the switch discards packets whose vid port membership in vlan table bits [18:16] does not include the ingress port. 0 = no ingress vlan filtering. 13 0 rw discard non pvid packets 1 = the switch discards packets whose vid does not match the ingress port default vid. 0 = no packets are discarded. 12 0 ro reserved 11 0 ro reserved 10 1 rw transmit enable 1 = enable packet transmission on the port. 0 = disable packet transmission on the port. 9 1 rw receive enable 1 = enable packet reception on the port. 0 = disable packet reception on the port. 8 0 rw learning disable 1 = disable switch address learning capability. 0 = enable switch address learning. 7 0 rw sniffer port 1 = port is designated as the sniffer port and transmits packets that are monitored. 0 = port is a normal port. 6 0 rw receive sniff 1 = all packets received on the port are marked as monitored packets and forwarded to the designated sniffer port. 0 = no receive monitoring. 5 0 rw transmit sniff 1 = all packets transmitted on the port are marked as monitored packets and forwarded to the designated sniffer port. 0 = no transmit monitoring. 4 0 rw reserved 3 0 rw user priority ceiling 1 = if the packets user priority field is greater than the user priority field in the port default tag register, replace the packets user priority field with the user priority field in the port default tag register. 0 = do no compare and replace the packets user priority field. 2-0 0x7 rw port vlan membership define the ports port vlan membership. bit 2 stands for host port, bit 1 for port 2, and bit 0 for port 1. the port can only communicate within the membership. a 1 includes a port in the membership; a 0 excludes a port from the membership. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 115 m9999-102207-1.9 bank 52 host port vid cont rol register (0x04): p3vidcr this register contains the global per port control for the sw itch function. see description in p1vidcr, bank 48 (0x04) bank 52 host port control register 3 (0x06): p3cr3 this register contains the global per port control for the switch function. see description in p1cr3, b ank 48 (0x06) bank 52 host port ingress rate control register (0x08): p3ircr this register contains per port ingress rate control. see description in p1ircr, bank 48 (0x08) bank 52 host port egress rate control register (0x0a): p3ercr this register contains per port egress rate control. see description in p1ercr, bank 48 (0x0a) banks 53 C 63: reserved except bank select register (0xe) downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 116 m9999-102207-1.9 mib (management information base) counters the ksz8842m provides 34 mib counters for each port. these counters are used to monitor the port activity for net work management. the mib counters are formatted per port as shown in table 14 and all ports dropped packet as shown in table 16. bit name r/w description default 31 overflow ro 1: counter overflow. 0: no counter overflow. 0 30 count valid ro 1: counter value is valid. 0: counter value is not valid. 0 29-0 counter values ro counter value (read clear) 0x00000000 table 14. format of per port mib counters per port mib counters are read using indirect memory access. the base address offsets and address ranges for both ethernet ports are: port 1, base address is 0x00 and range is from 0x00 to 0x1f. port 2, base address is 0x20 and range is from 0x20 to 0x3f. per port mib counters are read using indirect access control register in iacr, bank 42 (0x00) and indirect access data registers in iadr4[15:0], iadr5[31:16]. table 15 shows the port 1 mib counters address memory offset. offset counter name description 0x0 rxloprioritybyte rx lo-priority (default) octet count including bad packets 0x1 rxhiprioritybyte rx hi-priority octet count including bad packets 0x2 rxundersizepkt rx undersize packets w/ good crc 0x3 rxfragments rx fragment packets w/ bad crc, symbol errors or align ment errors 0x4 rxoversize rx oversize packets w/ good crc (max: 1536 or 1522 bytes) 0x5 rxjabbers rx packets longer than 1522 bytes w/ either crc errors, alignment errors, or symbol errors (depends on max packet size setting) 0x6 rxsymbolerror rx packets w/ invalid data symbol and legal packet size. 0x7 rxcrcerror rx packets within (64,1522) bytes w/ an integral number of bytes and a bad crc (upper limit depends on max packet size setting) 0x8 rxalignmenterror rx packets within (64,1522) bytes w/ a non-integral number of bytes and a bad crc (upper limit depends on max packet size setting) 0x9 rxcontrol8808pkts number of mac control frames received by a port with 88-08h in ethertype field 0xa rxpausepkts number of pause frames received by a port. pause frame is qualified with ethertype (88-08h), da, control opcode (00-01), data length (64b min), and a va lid crc 0xb rxbroadcast rx good broadcast packets (not including error broadcast packets or valid multicast packets) 0xc rxmulticast rx good multicast packets (not including mac control frames, error multicast packets or valid broadcast packets) 0xd rxunicast rx good unicast packets 0xe rx64octets total rx packets (bad packets included) that were 64 octets in length 0xf rx65to127octets total rx packets (bad packets included) that are between 65 and 127 octets in length 0x10 rx128to255octets total rx packets (bad packets included) that are between 128 and 255 octets in length 0x11 rx256to511octets total rx packets (bad packets included) that are between 256 and 511 octets in length 0x12 rx512to1023octets total rx packets (bad packets included) that are between 512 and 1023 octets in length downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 117 m9999-102207-1.9 offset counter name description 0x13 rx1024to1522octets total rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting) 0x14 txloprioritybyte tx lo-priority good octet count, including pause packets 0x15 txhiprioritybyte tx hi-priority good octet count, including pause packets 0x16 txlatecollision the number of times a collision is detected later than 512 bit-times into the tx of a packet 0x17 txpausepkts number of pause frames transmitted by a port 0x18 txbroadcastpkts tx good broadcast packets (not incl uding error broadcast or valid multicast packets) 0x19 txmulticastpkts tx good multicast packets (not including error multicast packets or valid broadcast packets) 0x1a txunicastpkts tx good unicast packets 0x1b txdeferred tx packets by a port for which the 1st tx attempt is delayed due to the busy medium 0x1c txtotalcollision tx total collision, half duplex only 0x1d txexcessivecollision a count of frames for which tx fails due to excessive collisions 0x1e txsinglecollision successfully tx frames on a po rt for which tx is inhibited by exactly one collision 0x1f txmultiplecollision successfully tx frames on a port for which tx is inhibited by more than one collision table 15. port 1 mib counters indirect memory offset format of all ports dropped packet mib counters bit default r/w description 30-16 - n/a reserved 15-0 0x0000 ro counter value table 16. all ports dropped packet mib counters format note: all ports dropped packet mib counters do not indicate overflow or validity; therefore, the application mus t keep track of overflow and valid conditions. all ports dropped packet mib counters are read using indirect memory access. the address offsets for these counters are shown in table 17. offset counter name description 0x100 port1 tx drop packets tx packets dropped due to lack of resources 0x101 port2 tx drop packets tx packets dropped due to lack of resources 0x103 port1 rx drop packets rx packets dropped due to lack of resources 0x104 port2 rx drop packets rx packets dropped due to lack of resources table 17. all ports dropped packet mib counters indirect memory offsets downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 118 m9999-102207-1.9 examples: 1. mib counter read (read port 1 rx64octets counter at indirect address offset 0x0e) write to reg. iacr with 0x1c0e (set indirect address and trigger a read mib counters operation) then read reg. iadr5 (mib counter value 31-16) // if bit 31 = 1, there was a counter overflow // if bit 30 = 0, restart (reread) from this register read reg. iadr4 (mib counter value 15-0) 2. mib counter read (read port 2 rx64octets counter at indirect address offset 0x2e) write to reg. iacr with 0x1c2e (set indirect address and trigger a read mib counters operation) then read reg. iadr5 (mib counter value 31-16) // if bit 31 = 1, there was a counter overflow // if bit 30 = 0, restart (reread) from this register read reg. iadr4 (mib counter value 15-0) 3. mib counter read (read port1 tx drop packets counter at indir ect address o ffset 0x100) write to reg. iacr with 0x1d00 (set indirect address and trigger a read mib counters operation) then read reg. iadr4 (mib counter value 15-0) additional mib information per port mib counters are designed as read clear. that is, these counters will be cleared after they ar e read. all ports dropped packet mib counters are not cleared after they are accessed. the application needs to keep track of overflow and valid conditions on these counters. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 119 m9999-102207-1.9 static mac address table the ksz8842m supports both a static and a dynamic mac address table. in response to a destination address (d a) look up, the ksz8842m searches both tables to make a packet forwarding decision. in response to a sourc e address (sa) look up, only the dynamic table is searched for aging, migration and learning purposes. the static da look up result takes precedence over the dynamic da look up result. if there is a da match in both tables, the result from the static table is used. these entries in the static table will not be aged out by the ksz8842m. bit default value r/w description 57-54 0000 rw fid filter vlan id - identifies one of the 16 active vlans. 53 0 r/w use fid 1: specifies the useof fid+mac for static table look ups 0: specifies only the use of mac for static table look ups 52 0 r/w override 1: overrides the port setting transmit enable = 0 or receive enable = 0 setting. 0: specifies no override 51 0 r/w valid 1: specifies that this entry is valid, the look up result will be used 0: specifies that this entry is not valid 50-48 000 r/w forwarding ports these 3 bits control the forwarding port(s): 000: no forward 001: forward to port 1 010: forward to port 2 100: forward to port 3 011: forward to port 1 and port 2 110: forward to port 2 and port 3 101: forward to port 1 and port 3 111: broadcasting (excluding the ingress port) 47-0 0 r/w mac address 48 bits mac address table 18. static mac table format (8 entries) static mac table lookup examples: 1. static address table read (read the second entry at indirect address offset 0x01) write to reg. iacr with 0x1001 (set indirect address and trigger a read static mac table operation) then read reg. iadr3 (static mac table bits 57-48) read reg. iadr2 (static mac table bits 47-32) read reg. iadr5 (static mac table bits 31-16) read reg. iadr4 (static mac table bits 15-0) 2. static address table write (write the eighth entry at indirect address offset 0x07) write to reg. iadr3 (static mac table bits 57-48) write to reg. iadr2 (static mac table bits 47-32) write to reg. iadr5 (static mac table bits 31-16) write to reg. iadr4 (static mac table bits 15-0) write to reg. iacr with 0x0007 (set indirect address and trigger a write static mac table operation) downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 120 m9999-102207-1.9 dynamic mac address table the dynamic mac address is a read only table. bit default value r/w description 71 ro data not ready 1: specifies that the entry is not ready, continue retrying until bit is set to 0 0: specifies that the entry is ready 70-67 ro reserved 66 1 ro mac empty 1: specifies that there is no valid entry in the table 0: specifies that there are valid entries in the table 65-56 0x000 ro no of valid entries indicates how many valid entries in the table 0x3ff means 1 k entries 0x001 means 2 entries 0x000 and bit 66 = 0 means 1 entry 0x000 and bit 66 = 1 means 0 entry 55-54 ro time stamp specifies the 2-bit counter for internal aging. 53-52 00 ro source port identifies the source port where fid+mac is learned: 00: port 1 01: port 2 10: port 3 51-48 0x0 ro fid specifies the filter id. 47-0 0x0000_0000_ 0000 ro mac address specifies the 48-bit mac address. table 19. dynamic mac address table format (1024 entries) dynamic mac address lookup example: dynamic mac address table read (read the first entry at indirect address offset 0 and retrieve t he mac table size) write to reg. iacr with 0x1800 (set indirect address and trigger a read dynamic mac table operation) then read reg. iadr1 (dynamic mac table bits 71-64) // if bit 71 = 1, restart (reread) from this register read reg. iadr3 (dynamic mac table bits 63-48) read reg. iadr2 (dynamic mac table bits 47-32) read reg. iadr5 (dynamic mac table bits 31-16) read reg. iadr4 (dynamic mac table bits 15-0) downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 121 m9999-102207-1.9 vlan table the ksz8842m uses the vlan table to perform look-ups. if 802.1q vlan mode is enabled (sgcr2[15]), this table will be used to retrieve the vlan information that is associated with the ingress packet. this information inclu des fid (filter id), vid (vlan id), and vlan membership as described in table 20: bit default value r/w description 19 1 rw valid 1: specifies that this entry is valid, the look up result will be used 0: specifies that this entry is not valid 18-16 111 r/w membership specifies which ports are members of the vlan. if a da look up fails (no match in both static and dynamic tables), the packet associated with this vlan will be forwarded to ports specified in this field. for example: 101 means port 3 and 1 are in this vlan. 15-12 0x0 r/w fid specifies the filter id. the ksz8842m supports 16 active vlans represented by these four bit fields. the fid is the mapped id. if 802.1q vlan is enabled, the look up will be based on fid+da and fid+sa. 11-0 0x001 r/w vid specifies the ieee 802.1q 12 bits vlan id. table 20. vlan table format (16 entries) if 802.1q vlan mode is enabled, then ksz8842m will assign a vid to every ingress packet. if the packet is untagged or tagged with a null vid, then the packet is assigned with the default port vid of the ingress port. if the packet is tagged with non null vid, then vid in the tag will be used. the look up process will start from the vlan table look up. if the vid is not valid, then packet will be dropped and no address learning will take place. if the vid is valid, then fid is retrieved. the fid+da and fid+sa lookups are performed. the fid+da look up determines the forwarding ports. if fid+da fails, then the packet will be broadcast to all the members (excluding the ingress port) of the vlan. if fid+sa fails, then the fid+sa will be learned. vlan table lookup examples: 1. vlan table read (read the third entry, at the indirect address offset 0x02) write to reg. iacr with 0x1402 (set indirect address and trigger a read vlan table operation) then read reg. iadr5 (vlan table bits 19-16) read reg. iadr4 (vlan table bits 15-0) 2. vlan table write (write the seventh entry, at the indirect address offset 0x06) write to reg. iadr5 (vlan table bits 19-16) write to reg. iadr4 (vlan table bits 15-0) write to reg. iacr with 0x1406 (set indirect address and trigger a read vlan table operation) downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 122 m9999-102207-1.9 absolute maximum ratings (1) description pins value supply voltage vddatx, vddarx, vddio C0.5v to +4.0v input voltage all inputs C0.5v to +5v output voltage all outputs C0.5v to +4.0v lead temperature (soldering, 10 sec) n/a 270 c storage temperature (ts) n/a C55 c to +150 c table 21. maximum ratings note: exceeding the absolute maximum rating may damage the device. stresses greater than those li sted in the table above may cause pe rmanent damage to the device. operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. unused inputs must alwa ys be tied to an appropriate lo gic voltage level. operating ratings (1) parameter symbol min typ max supply voltages vddatx,vddarx vddio 3.1v 3.1v 3.3v 3.3v 3.5v 3.5v ambient operating temperature t a 0 c +70c maximum junction temperature t j +125c thermal resistance junction-to-ambient (2) ja 42.91 c/w thermal resistance junction-to-case (2) jc 19.6 c/w table 22. operating ratings notes: 1. the device is not guaranteed to function outside its operating rating. unused inputs must always be tied to an appropria te l ogic voltage level (ground to vdd). 2. no (hs) heat spreader in this package. the jc / ja is under air velocity 0 m/s. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 123 m9999-102207-1.9 electrical characteristics (1) parameter symbol condition min typ max supply current for 100base-tx operation (2) (all ports@100% utilization) 100base-tx (analog core + pll + digital core + transceiver + digital i/o) i ddxio vddatx, vddarx, vddio = 3.3v; chip only (no transformer) 122ma supply current for 10base-t operation (2) (all ports@100% utilization) 10base-t (analog core + pll + digital core + transceiver + digital i/o) i ddxio vddatx, vddarx, vddio = 3.3v; chip only (no transformer) 90ma ttl inputs input high voltage v ih 2.0v input low voltage v il 0.8v input current i in v in = gnd ~ vddio -10 a 10 a ttl outputs output high voltage v oh i oh = -8 ma 2.4v output low voltage v ol i ol = 8 ma 0.4v output tri-state leakage |i oz | 10 a 100base-tx transmit (measured differentially after 1:1 transformer) peak differential output voltage v o 100 ? termination on the differential output. + 0.95v + 1.05v output voltage imbalance v imb 100 ? termination on the differential output 2% rise/fall time t r /t f 3ns 5ns rise/fall time imbalance 0ns 0.5ns duty cycle distortion + 0.25ns overshoot 5% reference voltage of iset v set 0.5v output jitter peak to peak 0.7ns 1.4ns 10base-t receive squelch threshold v sq 5mhz square wave 400mv 10base-t transmit (measured differentially after 1:1 transformer) peak differential output voltage v o 100 ? termination on the differential output 2.4v output jitter peak to peak 1.8ns 3.5ns table 23. electrical characteristics notes: 1. ta = 25c, specification for packaged product only. 2. a single ports transformer consumes an additional 45ma at 3.3v for 100base-t and 70ma a t 3.3v for 10base-t. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 124 m9999-102207-1.9 timing specifications asynchronous timing without using address strobe (adsn = 0) figure 17. asynchronous cycle C adsn = 0 symbol parameter min typ max unit t1 a1-a15, aen, bexn[3:0] valid to rdn, wrn active 0 ns a1-a15, aen, bexn[3:0] hold after rdn inactive (assume adsn tied low) 0 ns t2 a1-a15, aen, bexn[3:0] hold after wrn inactive (assume adsn tied low) 1 t3 read data valid to ardy rising 0.8 ns t4 read data to hold rdn inactive 4 ns t5 write data setup to wrn inactive 4 ns t6 write data hold after wrn inactive 2 ns t7 read active to ardy low 8 ns t8 write inactive to ardy low 8 ns ardy low (wait time) in read cycle (note1) (it is 0ns to read bank select register and 40ns to read qmu data register in turbo mode) (note2) 0 40 ns t9 ardy low (wait time) in read cycle (note1) (it is 0ns to read bank select register and 80ns to read qmu data register in normal mode) 0 80 ns t10 ardy low (wait time) in write cycle (note1) (it is 0ns to write bank select register) (it is 36ns to write qmu data register) 0 50 ns note 1 : when cpu finished current read or write operation, it can do next read or write operation even the ardy is low. during read or write operation if the adry is low, the cpu has to keep the rdn/wrn low until the ardy returns to high. note 2 : in order to speed up the ardy low time to 40 ns, user has to use the turbo software driver wh ich is only supported in the a6 device. please refer to the ksz88xx programmer's guide for detail. table 24. asynchronous cycle (adsn = 0) timing parameters t6 t5 t1 t4 t3 t2 valid valid valid a ddr, aen, bexn a dsn read data rdn, wrn write data t7 a rdy (read cycle) a rdy ( write cycle) t8 t9 t10 downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 125 m9999-102207-1.9 asynchronous timing using address strobe (adsn) t2 t7 t5 t4 t3 t1 t6 t8 valid valid valid a ddr, aen, bexn a dsn read data rdn, wrn write data a rdy (read cycle) a rdy ( write cycle) t9 t10 t11 figure 18. asynchronous cycle C using adsn symbol parameter min typ max unit t1 a1-a15, aen, bexn[3:0] valid to rdn, wrn active 0 ns t2 read data valid to ardy rising 0.8 ns t3 read data hold to rdn inactive 4 ns t4 write data setup to wrn inactive 4 ns t5 write data hold after wrn inactive 2 ns t6 a1-a15, aen, nbe[3:0] setup to adsn rising 4 ns t7 read active to ardy low 8 ns t8 a1-a15, aen, bexn[3:0] hold after adsn rising 2 ns t9 write inactive to ardy low 8 ns ardy low (wait time) in read cycle (note1) (it is 0ns to read bank select register and 40ns to read qmu data register in turbo mode) (note2) 0 40 ns t10 ardy low (wait time) in read cycle (note1) (it is 0ns to read bank select register and 80ns to read qmu data register in normal mode) 0 80 ns t11 ardy low (wait time) in write cycle (note1) (it is 0ns to write bank select register) (it is 36ns to write qmu data register) 0 50 ns note 1 : when cpu finished current read or write operation, it can do next read or write operation even the ardy is low. during read or write operation if the adry is low, the cpu has to keep the rdn/wr n low until the ardy returns to high. note 2 : in order to speed up the ardy low time to 40 ns, user has to use the turbo software driver wh ich is only supported in the a6 device. please refer to the ksz88xx programmer's guide for detail. table 25. asynchronous cycle using adsn timing parameters downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 126 m9999-102207-1.9 asynchronous timing using datacsn (ksz8842-32mql/mvl device only) t3 t7 t6 t5 t4 t1 t2 valid valid datacsn read data rdn, wrn write data a rdy (read cycle) a rdy ( write cycle) t8 t9 t10 figure 19. asynchronous cycle C using datacsn symbol parameter min typ max unit t1 datacsn setup to rdn, wrn active 2 ns t2 datacsn hold after rdn, wrn inactive (assume adsn tied low) 0 ns t3 read data hold to ardy rising 0.8 ns t4 read data to rdn hold 4 ns t5 write data setup to wrn inactive 4 ns t6 write data hold after wrn inactive 2 ns t7 read active to ardy low 8 ns t8 write inactive to ardy low 8 ns ardy low (wait time) in read cycle (note1) (it is 0ns to read bank select register and 40ns to read qmu data register in turbo mode) (note2) 0 40 ns t9 ardy low (wait time) in read cycle (note1) (it is 0ns to read bank select register and 80ns to read qmu data register in normal mode) 0 80 ns t10 ardy low (wait time) in write cycle (note1) (it is 0ns to write bank select register) (it is 85ns to write qmu data register) 0 50 ns note 1 : when cpu finished current read or write operation, it can do next read or write operation even the ardy is low. during read or write operation if the adry is low, the cpu has to keep the rdn/wr n low until the ardy returns to high. note 2 : in order to speed up the ardy low time to 40 ns, user has to use the turbo software driver wh ich is only supported in the a6 device. please refer to the ksz88xx programmer's guide for detail. table 26. asynchronous cycle using datacsn timing parameters downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 127 m9999-102207-1.9 address latching timing for all modes t3 t2 t1 ad sn address, aen, bexn ldevn figure 20. address latching cycle for all modes symbol parameter min typ max unit t1 a1-a15, aen, bexn[3:0] setup to adsn 4 ns t2 a1-a15, aen, bexn[3:0] hold after adsn rising 2 ns t3 a4-a15, aen to ldevn delay 5 ns table 27. address latching timing parameters downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 128 m9999-102207-1.9 synchronous timing in burst write (vlbusn = 1) figure 21. synchronous burst write cycles C vlbusn = 1 symbol parameter min typ max unit t1 swr setup to bclk falling 4 ns t2 datdcsn setup to bclk rising 4 ns t3 cyclen setup to bclk rising 4 ns t4 write data setup to bclk rising 6 ns t5 write data hold to bclk rising 2 ns t6 rdyrtnn setup to bclk falling 5 ns t7 rdyrtnn hold to bclk falling 3 ns t8 srdyn setup to bclk rising 4 ns t9 srdyn hold to bclk rising 3 ns t10 datacsn hold to bclk rising 2 ns t11 swr hold to bclk falling 2 ns t12 cyclen hold to bclk rising 2 ns table 28. synchronous burst write timing parameters downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 129 m9999-102207-1.9 synchronous timing in burst read (vlbusn = 1) t9 t8 t7 t6 t5 t4 t3 t1 t2 data0 data1 data2 data3 bclk datacsn swr cyclen read data rdyrtnn srdyn t11 t10 t12 figure 22. synchronous burst read cycles C vlbusn = 1 symbol parameter min typ max unit t1 swr setup to bclk falling 4 ns t2 datdcsn setup to bclk rising 4 ns t3 cyclen setup to bclk rising 4 ns t4 read data setup to bclk rising 6 ns t5 read data hold to bclk rising 2 ns t6 rdyrtnn setup to bclk falling 5 ns t7 rdyrtnn hold to bclk falling 3 ns t8 srdyn setup to bclk rising 4 ns t9 srdyn hold to bclk rising 3 ns t10 datacsn hold to bclk rising 2 ns t11 swr hold to bclk falling 2 ns t12 cyclen hold to bclk rising 2 ns table 29. synchronous burst read timing parameters downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 130 m9999-102207-1.9 synchronous write timing (vlbusn = 0) t12 t11 t10 t9 t8 t7 t4 t3 t6 t5 t1 t2 valid valid bclk ad d re s s , aen , bexn ad sn swr cyclen write data srdyn rdyrtnn figure 23. synchronous write cycle C vlbusn = 0 symbol parameter min typ max unit t1 a1-a15, aen, bexn[3:0] setup to adsn rising 4 ns t2 a1-a15, aen, bexn[3:0] hold after adsn rising 2 ns t3 cyclen setup to bclk rising 4 ns t4 cyclen hold after bclk rising (non-burst mode) 2 ns t5 swr setup to bclk 4 ns t6 swr hold after bclk rising with srdyn active 0 ns t7 write data setup to bclk rising 5 ns t8 write data hold from bclk rising 1 ns t9 srdyn setup to bclk 8 ns t10 srdyn hold to bclk 1 ns t11 rdyrtnn setup to bclk 4 ns t12 rdyrtnn hold to bclk 1 ns table 30. synchronous write (vlbusn = 0) timing parameters downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 131 m9999-102207-1.9 synchronous read timing (vlbusn = 0) t11 t10 t9 t8 t6 t7 t4 t3 t5 t1 t2 valid valid bclk ad d re s s , aen , bexn ad sn swr cyclen read data srdyn rdyrtnn figure 24. synchronous read cycle C vlbusn = 0 symbol parameter min typ max unit t1 a1-a15, aen, bexn[3:0] setup to adsn rising 4 ns t2 a1-a15, aen, bexn[3:0] hold after adsn rising 2 ns t3 cyclen setup to bclk rising 4 ns t4 cyclen hold after bclk rising (non-burst mode) 2 ns t5 swr setup to bclk 4 ns t6 read data hold from bclk rising 1 ns t7 read data setup to bclk 8 ns t8 srdyn setup to bclk 8 ns t9 srdyn hold to bclk 1 ns t10 rdyrtnn setup to bclk rising 4 ns t11 rdyrtnn hold after bclk rising 1 ns table 31. synchronous read (vlbusn = 0) timing parameters downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 132 m9999-102207-1.9 eeprom timing eesk eecs eedi eedo high-z d15 d14 d13 d1 d0 an a0 0 11 1 *1 *1 start bit tcyc ts th figure 25. eeprom read cycle timing diagram timing parameter description min typ max unit tcyc clock cycle 4 (obcr[1:0]=11 on-chip bus speed @ 25 mhz) or 0.8 (obcr[1:0]=00 on-chip bus speed @ 125 mhz) s ts setup time 20 ns th hold time 20 ns table 32. eeprom timing parameters downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 133 m9999-102207-1.9 auto negotiation timing figure 26. auto-negotiation timing timing parameter description min typ max unit t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulses per burst 17 33 table 33. auto negotiation timing parameters downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 134 m9999-102207-1.9 reset timing as long as the stable supply voltages to reset high timing (minimum of 10ms) are met, there is no power-sequencing requirement for the ksz8842m supply voltage (3.3v). the reset timing requirement is summarized in the figure 27 and table 34. figure 27. reset timing symbol parameter min max unit t sr stable supply voltages to reset high 10 ms table 34. reset timing parameters downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 135 m9999-102207-1.9 selection of isolation transformers a 1:1 isolation transformer is required at the line interface. an isolation transformer with integrated common-mode c hoke is recommended to exceed fcc requirements. table 35 gives recommended transformer characteristics. parameter value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min) 350 h 100mv, 100khz, 8ma leakage inductance (max) 0.4 h 1mhz (min) inter-winding capacitance (max) 12pf d.c. resistance (max) 0.9 ? insertion loss (max) 1.0db 0mhz C 65mhz hipot (min) 1500vrms table 35. transformer selection criteria magnetic manufacturer part number auto mdi-x number of port pulse h1102 yes 1 pulse (low cost) h1260 yes 1 transpower hb726 yes 1 bel fuse s558-5999-u7 yes 1 delta lf8505 yes 1 lankom lf-h41s yes 1 tdk (mag jack) tla-6t718 yes 1 table 36. qualified single port magnetic selection of reference crystal chacteristics value units frequency 25 mhz frequency tolerance (max) 50 ppm load capacitance (max) 20 pf series resistance 25 ? table 37. typical reference crystal characteristics downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 136 m9999-102207-1.9 package information figure 28. 128-pin pqfp package. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 137 m9999-102207-1.9 figure 29. optional 128-pin lqfp package downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 138 m9999-102207-1.9 figure 30. optional 100-ball lfbga package downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 139 m9999-102207-1.9 acronyms and glossary biu bus interface unit the host interface function that performs code conversion, buffering, and the like required for communications to and from a network. bpdu bridge protocol data unit a packet containing ports, addresses, etc. to make sure data being passed through a bridged network arrives at its proper destination. cmos complementary metal oxide semiconductor a common semiconductor manufacturing technique in which positive and negative types of transistors are combined to form a current gate that in turn forms an effective means of controlling electrical current through a chip. crc cyclic redundancy check a common technique for detecting data transmission errors . crc for ethernet is 32 bits long. cut-through switch a switch typically processes received packets by reading in the full packet (storing), then processing the packet to determine where it needs to go, then forwarding it. a cut-through switch simply reads in the first bit of an incoming packet and forwards the packet. cut-through switches do not store the packet. da destination address the address to send packets. dma direct memory access a design in which memory on a chip is controlled independently of the cpu. eeprom electronically erasable programmable read-only memory a design in which memory on a chip can be erased by exposing it to an electrical charge. eisa extended industry standard architecture a bus architecture designed for pcs using 80x86 processors, or an intel 80386, 80486 or pentium microprocessor. eisa buses are 32 bits wide and support multiprocessing . emi electro-magnetic interference a naturally occurring phenomena when the electromagnetic field of one device disrupts, impedes or degrades the electromagnetic field of another device by coming into proximity with it. in computer technology, computer devices are susceptible to emi because electromagnetic fields are a byproduct of passing electricity through a wire. data lines that have not been properly shielded are susceptible to data corruption by emi. fcs frame check sequence see crc. fid frame or filter id specifies the frame identi fier. alternately is the filter identifier. igmp internet group management protocol the protocol defined by rfc 1112 for ip multicast transmissions. ipg inter-packet gap a time delay between successive data packets mandated by the network standard for protocol reasons. in ethernet, the medium has to be "silent" (i.e., no data transfer) for a short period of time before a node can consider the network idle and start to transmit. ipg is used to correct timing differences between a transmitter and receiver. during the ipg, no data is transferred, and information in the gap can be discarded or additions inserted without impact on data integrity. isi inter-symbol interference t he disruption of transmitted code caused by adjacent pulses affecting or interfering with each other. isa industry standard architecture a bus architecture used in the ibm pc/xt and pc/at . jumbo packet a packet larger than the standard ethernet packet (1500 bytes). large packet sizes allow for more efficient use of bandwidth, lower overhead, less processing, etc. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 140 m9999-102207-1.9 mdi medium dependent interface an ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. mdi provides the standard interface to a particular media (copper or fiber) and is therefore 'media dependent.' mdi-x medium dependent interface crossover an ethernet port connection that allows networked end stations (i.e., pcs or workstations) to connect to each other using a null-modem, or crossover, cable. for 10/100 full-duplex networks, an end point (such as a computer) and a switch are wired so that each transmitter connects to the far end receiver. when connecting two computers together, a cable that crosses the tx and rx is required to do this. with auto mdi-x, the phy senses the correct tx and rx roles, eliminating any cable confusion. mib management information base the mib comprises the management portion of network devices. this can include things like monitoring traffic levels and faults (statistical), and can also change operating parameters in network nodes (static forwarding addresses). mii media independent interface the mii accesses phy registers as defined in the ieee 802.3 specification. nic network interface card an expansion board inserted into a computer to allow it to be connected to a network. most nics are designed for a particular type of network, protocol, and media, although some can serve multiple networks. npvid non port vlan id the port vlan id value is used as a vlan reference. pll phase-locked loop an electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or reference, signal. a pll ensures that a communication signal is locked on a specific frequency and can also be used to generate, modulate, and demodulate a signal and divide a frequency. pme power management event an occurrence that affects the directing of power to different components of a system. qmu queue management unit manages packet traffic between mac/phy interface and the system host. the qmu has built-in packet memories for receive and transmit functions called txq (transmit queue) and rxq (receive queue). sa source address the address from which information has been sent. tdr time domain reflectometry tdr is used to pinpoint flaws and problems in underground and aerial wire, cabling, and fiber optics. they send a signal down the conductor and measure the time it takes for the signal -- or part of the signal -- to return. utp unshielded twisted pair commonly a cable containing 4 twisted pairs of wires. the wires are twisted in such a manner as to cancel electrical interference generated in each wire, therefore shielding is not required. vlan virtual local area network a configuration of comput ers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere. downloaded from: http:///
micrel, inc. ksz8842-16/32 mql/mvl/mvli/mbl october 2007 141 m9999-102207-1.9 appendix the 1.2v ldo output (pin 24) sometimes unable reaches to 1.2v level and stay at <0.6v due to high temperature (>50c) or 3.3v supply ramps up too slow. we recommend that by adding a 100-ohm resistor between 1.2v a nd 3.3v to prevent this problem, this will ensure that our device can work with wider range of supplies and temperatures as s hown below: 100 (0603-1/8w) 3.3v (pin 92 ) 1.2v (pin 91 ) micrel, inc. 2180 fortune drive san jose, ca 95131 us a tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. how ever, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time wi thout notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or s ystems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or system s that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonabl y expected to resul t in a significant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is a pu rchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sa le. ? 2004 micrel, incorporated. downloaded from: http:///

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